本論文主要以標準台積電(TSMC)SiGe BiCMOS與0.18 um CMOS製程技術，並利用三種不同的電路架構來設計應用於K-band的倍頻器。第一個設計以台積電0.18 um SiGe BiCMOS製程實現一新型的平衡式架構8-24 GHz三倍頻器，此倍頻器於輸出端利用主動式巴倫電路來改善傳統平衡式架構因使用耦合器使得佈局面積過大且限制了調整相位延遲的缺點。第二個設計以台積電0.18 um CMOS製程實現應用主動式轉導提昇共閘極電路技術的12-24 GHz二倍頻器，倍頻器電路以共閘極為主要設計架構，並以一共源極放大器來實現此一轉導提昇級，以提升倍頻器的轉換增益。第三個設計同以台積電0.18 um CMOS製程實現電流再利用電路技術的8-24 GHz三倍頻器，電路中於第二級NMOS電晶體的源極端加入一適當電阻接地以提供而外的電流路徑，如此改善倍頻器在非常小功率輸入條件下的轉換增益，且避免電流的浪費。;This thesis presents the design of K-band frequency multipliers by three circuit topologies in TSMC standard SiGe BiCMOS and 0.18 um CMOS process. In the first design of thesis, we present a new configuration of a balanced 8-24 GHz tripler in TSMC SiGe BiCMOS process. Because of the conventional balanced frequency multipliers usually used couplers and the couplers are too large in dimensions and also limit the phase delay function. So to improve this, the output part of this frequency tripler has been changed by an active balun to instead of the coupler. In the second design of thesis, we present an active Gm-boosted common-gate 12-24 GHz doubler in TSMC 0.18 um CMOS process, the design employs a common-gate configuration and utilizing the common-source configuration as Gm-boosted stage to raise the conversion gain of the doubler. In the third design of thesis, we present an 8-24 GHz tripler with current-reuse technique in TSMC 0.18 um CMOS process, the circuit of tripler places a bypass resistor between common ground and the source node of the second stage NMOS transistor to provide an additional current path and thus improving conversion gain and input power level while saving the waste of current consumption.