中大機構典藏-National Central University (Taiwan) Institutional Repository-提供博碩士論文、考古題、期刊論文、研究計畫等下載:Item 987654321/65787
English  |  正體中文  |  简体中文  |  Items with full text/Total items : 65317/65317 (100%)
Visitors : 21364679      Online Users : 352
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version


    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/65787


    Title: 基於自適性稀疏表示之影像顯著度偵測系統超大型積體電路設計;VLSI Architecture Design for Saliency Detection Based on Self-adaptive Sparse Representation
    Authors: 林彥宇;Lin,Yan-yu
    Contributors: 資訊工程學系
    Keywords: 稀疏表示;K-SVD;顯著度偵測
    Date: 2014-08-21
    Issue Date: 2014-10-15 17:10:22 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 本篇論文提出了一個高效能的VLSI架構來實現基於自適性稀疏表示的影像顯著度偵測系統。顯著度偵測是一項建立在人類視覺系統上的重要技術,在本論文中將此系統分為兩個處理階段:特徵表示階段與顯著度測量階段。此二階段在顯著度模型上皆是相當重要的研究課題,如何提出較好的特徵表示法及適當的顯著度測量法更是視覺顯著度模型中的核心問題。在眾多的研究中,稀疏表示已經能夠正確地表示出一個信號的重要部分,所以本研究在特徵表示的選擇上使用稀疏表示法。
    在系統流程中,特徵表示階段利用K-SVD演算法來找出資料的稀疏特徵,而在顯著度測量階段利用每個稀疏特徵找出其Background Firing Rate (BFR),再以Feature Activation Rate (FAR)完成此Bottom-up顯著度偵測系統。
    本論文所提出的晶片設計中包含了一個K-SVD模組、一個OMP模組、一個BFR模組和一個FAR模組。晶片的電路設計實現於TSMC 90 nm CMOS Technology,整體的晶片面積約為2.42×2.42 mm2。
    ;This work proposes an efficient VLSI architecture to perform saliency detection based on sparse representation approach. Saliency detection is a very important technology in the human visual system. Representation and measurement are two important issues for saliency models, and good representation is a critical issue in modelling visual saliency mechanism. Sparse representation has been shown to correctly represent an important part of the signal in a number of studies. This paper utilizes K-SVD algorithm for the feature representation stage, and in saliency measurement stage, background firing rate (BFR) is for each sparse feature and then feature activation rate (FAR) completes the bottom-up saliency detection. The proposed chip comprises a K-SVD module, an OMP module, a BFR module, and a FAR module. The prototype chip is a semi-custom chip that is fabricated using TSMC 90 nm CMOS technology on a die with a size of approximately 2.42x2.42 mm2.
    Appears in Collections:[Graduate Institute of Computer Science and Information Engineering] Electronic Thesis & Dissertation

    Files in This Item:

    File Description SizeFormat
    index.html0KbHTML267View/Open


    All items in NCUIR are protected by copyright, with all rights reserved.

    社群 sharing

    ::: Copyright National Central University. | 國立中央大學圖書館版權所有 | 收藏本站 | 設為首頁 | 最佳瀏覽畫面: 1024*768 | 建站日期:8-24-2009 :::
    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - Feedback  - 隱私權政策聲明