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    請使用永久網址來引用或連結此文件: http://ir.lib.ncu.edu.tw/handle/987654321/66115


    題名: 含多重檢查機制之實體驗證自動化工具;An Automated Utility with Multi-Checking Mechanism for Physical Verification
    作者: 吳建興;Wu,Chien-Hsing
    貢獻者: 電機工程學系在職專班
    關鍵詞: 實體驗證;Physical Verification
    日期: 2014-10-21
    上傳時間: 2014-11-24 15:45:36 (UTC+8)
    出版者: 國立中央大學
    摘要: 近年來,製程微縮的速度之快,目前己經進展到二十八奈米製程量產的階段。由於實體驗證 ( physical verification, PV ) 在積體電路設計中,被視為影響晶片下線 ( tape-out ) 時間之重要因素之一,因此各種電子設計自動化 ( electronic design automation, EDA ) 工具皆不斷地在提升其效能與檢查能力,以防止產品出錯。
    在目前的實體驗證過程中,由於設計者無法第一次就提供正確完整的網表 ( netlist ),因此執行實體驗證的佈局者必須不斷地重覆執行驗證與除錯。此外,晶圓廠 ( foundry ) 提供了設計規則檢查 ( design rule check, DRC ) 與佈局比對圖表 ( layout versus schematic, LVS ) 以及相關的檔案,其中包含了許多選擇性的設定供客戶使用,因此佈局者需要自行選擇複雜的設定與判斷除錯的結果。基於以上兩點,實體驗證流程需要一個完整的檢查機制來解決這些問題,以防止佈局者因個人誤判而導致產品出錯的情況發生。
    在本篇論文中,我們提出一個具有多重檢查機制的自動化工具,其建構在實體驗證的環境中。在考慮錯誤報告的資料量大小與資料分佈的特性下,截取特定資訊與圖形資料系統 ( graphic database system, GDS ) 及相關設定資訊進行多重的比對,並輸出一份關鍵詳細報告。實驗結果顯示,此工具能有效地檢查是否在實體驗證中有除錯不完全及設定不正確的情況發生。;In recent years, the manufacturing process shrinks quickly. The technology node of mass production is achieved 28 nanometer. Due to physical verification (PV) in IC design is one of the important factors affecting the time to tape-out, electronic design automation (EDA) tools are constantly improving their effectiveness and ability to prevent product failures.
    In the current physical verification process, because designers cannot provide a correct and complete netlist at the first time, layout engineers of physical verification need to perform validation and debugging constantly. In addition, foundries provide design rule check (DRC), layout versus schematic (LVS), and related files for designs, which contain several optional configurations for use, therefore layout engineers need to choose manually the complex configurations and judge the debugging results. Based on the above two issues, the flow of physical verification requires a complete checking mechanism to solve these issues to prevent production failures caused by the personal misjudgment of layout engineers.
    In this thesis, we propose an automated utility with multi-checking mechanism, which is constructed in the physical verification environment. With considering the characteristics of the data size and distribution of debugging reports, the proposed utility intercepts the specific information, graphic database system (GDS), and related configuration information to apply multiple comparisons and generate a critical detail report. Experimental results showed that the proposed utility can effectively check the incomplete debugging and incorrect configurations in the physical verification.
    顯示於類別:[電機工程學系碩士在職專班] 博碩士論文

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