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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/66896


    Title: 應用於系統晶片隨機存取記憶體之自我修復技術與規劃架構;Built-in self-repair technique and planning framework for RAMs in SoCs
    Authors: 侯致聖;Hou,Chih-Sheng
    Contributors: 電機工程學系
    Keywords: 記憶體;隨機存取記憶體;內建自我修復電路;memory;RAM;BISR
    Date: 2014-12-04
    Issue Date: 2015-03-16 15:58:45 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 先進系統晶片(SoC)具有上百個以具侵略性的隨機存取記憶體(random access memory),然而這些隨機存取記憶體通常佔據著絕大部分矽晶片的面積,也因此系統晶片中內嵌式(embedded)記憶體的良率(yield)嚴重地影響系統晶片的良率,有效的記憶體良率提升技術是相當重要。內建自我修復電路(built-in self-repair, BISR) 廣泛地使用於系統晶片內記憶體之修復。由於大量的記憶體存在於系統晶片之中,如何有效地提升記憶體修復效率、降低測試暨修復時間、以及縮小內建自我修復電路之硬體成本皆是相當重要的議題。
    在論文中第一部分提出一個高修復效率之記憶體內建自我修復界面(high-repair-efficiency BISR, HRE-BISR),藉由重覆使用一個區域型的位元地圖(local bitmap)在正常操作模式下(normal mode)達成修復元件之功能以此方式修復更多記憶體內部之瑕疵。首先我們提出一個重覆使用區域型位元地圖達成備份位元之記憶體內建自我修復界面(HRE-BISR-SB),搭配著一個行/列/位元之備份元件分析演算法(row/column/bit redundancy analysis algorithm)配置其內部汁備份元件。模擬結果顯示相較於傳統內建自我修復電路在各種不同的錯誤分布情況下(fault distribution),其HRE-BISR-SB介面可額外提升0.48%~11.95%的修復效率,另一方面,一個重覆使用區域型位元地圖達成備份字組(word)之記憶體內建自我修復界面(HRE-BISR-SW),相較於無重複使用技術的內建自我修復界面,其HRE-BISR-SW介面可額外提升0.71%~5.55%的修復效率。為了能夠有效地尋找最佳的備份元件配置的方式,因此提出一個最小備份元件尋找演算法以此搜尋最小硬體成本的配置方案。
    在論文中第二部分提出一個以修復效率為基準的記憶體測試排程技術,藉此方式在一個限定測試功率之情況下縮短具有內建自我修復電路之記憶體的測試暨修復時間。因此,根據其修復效率所計算出之提早中止機率(early abort probability),我們提出高效率測試排程演算法來達成上述目標。實驗結果顯示,所提出的高效率測試排程演算法可以縮短記憶體測試暨修復時間,以ITC’02實驗樣本(ITC’02 benchmark)為例子,相較於現存的記憶體排程演算法,本演算法可以平均降低10.7%之預估測試暨修復時間。
    在論文中第三部分提出一個運用分享式記憶體內建自我修復電路於系統晶片中記液體內建自我修復電路規劃企劃(memory BISR planning framework, MBiP),首先,在MBiP中具有記憶體群組化演算法(memory grouping algorithm)來達到挑選記憶體共享一個分享式記憶體內建自我修復電路。緊接著,依據測試排程演算法與記憶體群組演算法之結果,記憶體內建自我修復電路配置演算法(BISR scheme allocation algorithm)用於配置不同型態的分享式記憶體自我修復電路。實驗結果顯示,相較於獨立式記憶體內建自我修復電路(dedicated BISR),針對50個記憶體在350mW測試功率與1.5mm繞線距離之限制情況下,藉由MBiP配置記憶體內建自我修復電路的硬體成本可以減少22%。最後,考量存在著不同前建結測試(pre-bond test)與後建結測試(post-bond test)下的測試功率,MBiP拓展至規畫記憶體內建自我修復電路於三維積體電路內系統晶片之記憶體。實驗結果顯示,相較於獨立式記憶體內建自我修復電路(dedicated BISR),在500mW前建結測試功率、600mW後建結測試功率與1mm繞線距離之限制情況下,藉由MBiP配置記憶體內建自我修復電路的硬體成本可以減少35%。
    ;Modern system-on-chips (SoCs) typically encompass several hundreds of random access memory
    (RAM) cores designed with aggressive design rules. Those memory cores usually represent
    a significant portion of the chip area. Therefore, the yield of memory cores has heavy
    impact on the SoC yield. Effective yield-enhancement techniques for those memory cores
    thus are imperative. Built-in self-repair (BISR) technique has been widely used to repair
    the memory cores in SoCs. Since a large amount of RAMs are distributed in a SoC, how to
    boost the repair efficiency, minimize test and repair time, and minimize area cost of BISR
    circuits is an important issue.
    In the first part of this thesis, a high-repair-efficiency BISR scheme (HRE-BISR) is proposed.
    The HRE-BISR reuses a local bitmap to serve as redundancy elements in normal mode
    such that it can repair more faults. First, a HRE-BISR scheme reusing the local bitmap as
    spare bits (HRE-BISR-SB) is presented. In addition, a row/column/bit redundancy analysis
    algorithm is proposed to allocate redundancies of a RAM with the HRE-BISR-SB scheme.
    Simulation results show that the proposed HRE-BISR-SB scheme can provide 0.48%–11.95%
    increment of repair rate than a typical BISR scheme without reusing the local bitmap as
    spare bits for different fault distributions. Secondly, a HRE-BISR scheme reusing the local
    bitmap as spare words (HRE-BISR-SW) is presented, which can provide 0.71%–5.55% increment
    of repair rate than a BISR scheme without reusing the local bitmap as spare words.
    Finally, a minimal redundancy configuration searching algorithm is proposed to find a redundancy
    configuration with minimal area cost for a RAM with HRE-BISR scheme under
    a targeted repair rate.
    In the second part of this thesis, a repair-rate-driven test scheduling technique is proposed
    to minimize the test and repair time of RAMs with BISR circuits under the constraint of
    maximum power consumption. An efficient test scheduling algorithm based on the earlyabort
    probability calculated according to the repair rate is proposed. Simulation results show
    that the proposed algorithm can achieve smaller test and repair time than existing works.
    For ITC’02 benchmarks, for example, about 10.7% average reduction of expected test and
    repair time can be achieved by the proposed algorithm.
    In the third part of this thesis, a memory BISR planning (MBiP) framework is proposed
    to plan shared BISR schemes for the RAMs in a SoC. The MBiP framework consists of a
    memory grouping algorithm to select RAMs which can served by a shared BISR circuit.
    Then, a BISR scheme allocation algorithm is proposed to allocate different shared BISR
    schemes for the RAMs under the constraints of the results of memory grouping and a test
    scheduling. Simulation results show that, about 22% area reduction can be achieved by
    the proposed MBiP framework for 50 RAMs under 1.5mm distance constraint and 350mW
    test power constraint in comparison with a dedicated BISR scheme. Finally, we extend the
    MBiP framework to support the planning of shared BISR schemes for RAMs in SoC dies of
    three-dimensional ICs by considering the constraints of pre-bond and post-bond test power
    constraints. Simulation results show that 35% area reduction can be achieved by the shared
    BISR scheme planned by the proposed planning technique under 1mm distance constraint,
    500mW pre-bond test power, and 600mW post-bond test power constraints in comparison
    with a dedicated BISR scheme.
    Appears in Collections:[電機工程研究所] 博碩士論文

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