| 摘要: | 在本論文中，主要研究在SOI基板上開發三維光學網路，並將其應用於晶片等級的光學連接模組。本研究可區分為三個主題：點對點的三維光路架構、具有垂直分光器或垂直轉換結構的三維光路網路、以及在SOI基板上實現具有雷射與光偵測器的晶片等級光連接模組。藉由三維光學網路的開發，光路與電路可利用相容的製程技術分別建構在SOI基板的正反兩側。此外經由獨特的光電分離架構，光電元件與光子元件可以非常容易地與電子元件整合在單一矽晶片上，並且實現高傳輸速度與低功耗的晶片等級光學連接模組。
在點對點的三維光路之研究上，我們利用非等向性的濕蝕刻技術，將高品質的45˚微反射面與單晶矽梯形波導建構在SOI基板的光學元件層。藉由三維光路的設計，我們可同時解決三項問題，包含光源與光偵測器的整合、低損耗的單晶矽波導、以及光電分離式的整合設計。經由量測結果得知，從入射端單模光纖到出射端多模光纖的光學傳輸效率約為-2.91 dB，長直光波導的傳播損耗約為0.404 dB/cm。同時我們也驗證光纖對於此三維光路的位移容忍度，其中入射端單模光纖對於光波導的位移容忍度可大於±5 μm；出射端多模光纖對於光波導的位移容忍度可大於±14 μm。如此寬鬆的位移容忍度將有助於主動元件在量產時的封裝可行性。此外相較於傳統利用乾蝕刻技術製作的脊狀波導，本架構的光波導具有成本與量產可行性的優勢。
在第二個部分，為了提升三維光路的靈活性，我們提出應用於垂直分光波導的三維分光器，以及應用於主動式光學網路的垂直轉換結構。在三維垂直分光器部分，其原理是利用主波導與分光波導的幾何寬度差異，並且在其中插入單石積體化且具有45˚微反射面的垂直分光器。此結構可同時完成垂直分光，以及電子層與光學元件層的光學訊號連接。在此研究中，我們實現一個具有不同分光比例的三維1×2垂直分光波導。當主波導的波導寬度從40 μm變換至70 μm，垂直分光效率可從20%:80%轉換至46%:54%，總體的光學傳輸效率約為-6 dB。在此結構中，光波導具有較寬鬆的元件封裝位移容忍度(約大於±13 µm at -1 dB)，適合應用於被動式的光學網路架構。
針對應用於主動式光學網路的垂直轉換結構，我們將其製作於三維光波導的表面。此垂直轉換結構不僅可以實現光路的垂直轉換，並且可以提供一個光學平台，將可電控式多重量子井(MQWs)整合於此垂直轉換結構上。在本研究中，我們實現一個1×3垂直轉換光路，並且利用紅外光攝影機觀察光波導輸出端的光點。其總光學耦合效率約為-5.33 dB，各個通道出口的耦合效率約為-10.81、-11.74、以及-8.45 dB。長直光波導的傳播損耗約為0.178 dB/cm。相較於長直光波導，本架構的1×3垂直轉換光路的總分光損耗約為1.57 dB。
最後，我們在SOI基板上實現一個具有雷射、光偵測器、驅動電路、以及放大電路的晶片等級光學連接模組。在本模組中，我們利用獨特的三維光路設計，連接模組發射端與接收端，面射型雷射與光偵測器則利用覆晶封裝技術將其整合至SOI基板的電子元件層上，形成完整的光學連接模組。從量測結果得知，雷射至光偵測器的光學耦合效率約為-2.19 dB，雷射的最大輸出光功率與最低臨界電流分別為3.27 mW以及1 mA。在高速訊號的測試中，當最低的雷射驅動電流為9mA時，我們成功驗證一個10-Gbps的無錯誤訊號傳輸(Error-Free)。經由實驗量測證實，本論文所提出的三維光學網路可用以實現一個高速傳輸且低功耗的晶片等級光學連接模組。
;In this dissertation, the researches focus on the development of SOB-based 3-D network optical path for chip-level optical interconnects. The researches can be divided into three major topics, including the point-to-point 3-D optical path, the flexible 3-D network optical path with vertical power splitter and vertical transition structure, and the implementation of SOI-based chip-level optical interconnects with lasers and PDs. Using 3-D network optical path, the electronic and optical circuits can be respectively built on the rear (electronics layer) and front (optics layer) side of SOI substrate using compatible fabrication process. Because of the unique separated photonics-electronics design, active photonics devices and passive optics can be easily integrated with electronics circuits in a single silicon chip, and the high-speed data transmission with low power consumption for chip-level optical interconnects can be also achieved.
With respect to the research on the point-to-point 3-D optical path, the high-quality 45˚ micro-reflectors and crystalline silicon trapezoidal waveguides is realized on the SOI substrate using anisotropic wet-etching process. Using the 3-D optical path, there are three kinds of capability can be achieved, including the integration of high efficient laser and PD chips, the low-loss crystalline silicon waveguides, and the separated photonics-electronics design. From the measurement result, the transmission efficiency from input SMF to output MMF is -2.91 dB, and the propagation loss of silicon straight trapezoidal waveguides is as low as 0.404 dB/cm. A wide alignment tolerance of SMF-to-waveguide (> ±5 μm) and waveguide-to-MMF (> ±14 μm) is also achieved to facilitate the active device assembly. As compared to the conventional ridge waveguide using the dry-etching approach, the proposed 3-D optical path would be a cost-effective structure for the mass production.
In the second part of this dissertation, we proposed the 3-D power splitter for vertically-splitting waveguide and the vertical transition structure for active network optical path. Respect to the vertically-splitting waveguide, it is designed by the concept of using waveguide width difference between bus waveguide and branch waveguide. The monolithically embedded vertically-splitting structure with sidewall angle of 45˚ is used to vertically split the light and simultaneously connect the optics layer with the electronics layer of SOI substrate in the proposed chip-level optical interconnect systems. In this research, we experimentally demonstrated the 3-D 1×2 vertically-splitting waveguide with various power splitting ratios. The total transmission efficiency of proposed waveguide is around -6 dB, and the power splitting ratio of optical path 1 to optical path 2 can be controlled from 20%:80% to 46%:54% as the upper width of bus waveguide adjusts from 40 to 70 μm. The proposed vertically-splitting waveguide also provides the wider alignment tolerance (larger than ±13 µm at -1 dB power variation) for the active photonics device assembly.
The vertical-transition structures with 45˚ sidewall angle are first demonstrated in the SOI-based 3-D optical path. Such unique vertical-transition structures not only perform the vertical transition optical path but also provide a stage to integrate with the electrically controlled electro-absorption MQWs that is used to actively switch the optical path. Here, we experimentally demonstrated the 1×3 vertical-transition optical waveguide. Three clear light spots emitting from each output ports are observed by an IR camera. The total optical transmission efficiency can reach to -5.33 dB, and the corresponding optical transmission efficiency at output port 1, 2, and 3 are -10.81, -11.74, and -8.45 dB, respectively. A lower propagation loss of 0.178 dB/cm is also demonstrated by the cut-back method. Compared to the straight waveguide without any vertical-transition structures, the total splitter loss of 1×3 vertical-transition straight waveguide is 1.57 dB.
Finally, we first demonstrated the chip-level optical interconnect module combined with a VCSEL chip, a PD chip, a driver IC, and an amplifier IC on a SOI substrate. The unique point-to-point 3-D optical path is used to connect optical signal between transmitter and receiver. In this research, the VCSEL and PIN PD chips are flip-chip integrated on the electrical layer of SOI substrate to achieve complete chip-level optical interconnects. A higher VCSEL-to-PD optical coupling efficiency of -2.19 dB, a maximum optical power of 3.27 mW, and a low threshold current of 1 mA are achieved. The error-free data transmission of 10-Gbps can be also demonstrated when VCSEL is operated at the driving current of 9 mA. These measurement results verify that the proposed chip-level optical interconnect could be operated at a higher data rate and a lower power consumption using the proposed SOI-based 3-D optical paths. |
