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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/68725

    Title: 鉭錳合金及銅鍺化合物應用於積體電路後段製程中銅導線之研究;The application of tantalum-manganese alloy and copper-germanide on copper interconnect in back-end module of integrated circuit
    Authors: 林坤彥;Lin,Kun-Yan
    Contributors: 電機工程學系
    Keywords: 銅導線;可靠度;擴散阻擋層;Cu interconnect;reliability;diffusion barrier
    Date: 2015-07-01
    Issue Date: 2015-09-23 14:22:37 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 摘要

    根據摩爾定律(Moore′s Law)指出,積體電路上可容納電晶體數目,約每隔24個月就會增加一倍,隨著元件尺寸的不斷縮小,晶片運作速度不只受限於電晶體本身電性功能,亦受到金屬導線傳遞訊號速度的影響,因此後段連線系統中的時間延遲(RC Delay)就會變成限制積體電路發展的主要原因之一[1],為了提高導線的傳輸速率,因此採用低電阻的銅取代鋁,同時銅導線的抗電致遷移能力也比鋁更好,可以提高IC電路的可靠性,但銅的擴散係數很高,很容易擴散到基材。在快速縮小銅導線寬度同時又要承受更高的電流密度,電致遷移效應與擴散阻擋會是要面對的主要問題[2]。
    本論文中的實驗使用微影製程製作出銅導線,嘗試使用TaMn 合金作為擴散阻擋層材料及以Cu3Ge合金作為電鍍晶種層材料,在高電流密度與高溫下量測銅導線在不同的測試結構下的失效時間,藉此求出個別的活化能(activation energy)與電流加速因子(current acceleration factor),並和Ta/TaN比較,並討論不同的擴散阻擋層對於銅導線可靠度的影響,分析造成元件失效的原因。

    According to Moore’s Law, the number of transistors in the integrated circuit has double approximately every twenty-four months. With the scaling of feature size, the performance of chips will be limited not only by the electrical performance of the transistors but also by the transmission rate of interconnect. Therefore, the RC delay of back-end interconnect will be one of main issue for limiting the development of integrated circuit. [1] To enhance the transmission rate of interconnect, aluminum was replaced with copper which has lower resistivity and better ability against eletromigration. As a result, it could enhance the performance of integrated circuit. However, the diffusion coefficient of copper is very large, and it is easy for copper to diffuse into silicon substrate. It is a great issue that how to enhance diffusion barrier and electromigration when we scale down the width of interconnect and hold up high current density. [2]

    In the research, lithography and deposition process were employed to fabricate interconnect with TaMn alloy as diffusion barrier and Cu3Ge alloy as seed layer of plating. The failure time of different test structure was measured by high current density and high temperature. By this method, the activation energy and current acceleration factor can be obtained. To compare with the samples with diffusion barrier of TaN/Ta, interconnect reliability with different diffusion barriers and seeding layer was summarized and the mechanism of the failure mode was analyzed.
    Appears in Collections:[電機工程研究所] 博碩士論文

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