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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/68767

    Title: 一個寬頻鎖相迴路具有全域操作的高線性度壓控振盪器;A Wide Band PLL with A High Linearity VCO in Full Range
    Authors: 奚國綱;Hsi,Kuo-kang
    Contributors: 電機工程學系在職專班
    Keywords: 寬頻;鎖相迴路;全域;線性度;振盪器;Wide Band;PLL;Linearity;VCO;Full Range
    Date: 2015-08-21
    Issue Date: 2015-09-23 14:25:35 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 近年來超大型積體電路蓬勃發展,電路的效能及速度也隨著製程技術的精進而提升,且目前的晶片皆趨向整合成單晶片系統(System-on-Chip),所以在整合系統中各個子電路
    的特性式 f=Kvco•Vctrl+fmin 的正確性,其中的關鍵點在於壓控振盪器的偏壓電路,
    80MHz~160MHz 的頻率範圍皆能正確鎖定。
    本論文以CIC CMOS 0.18um 1P6M 虛擬製程來實現,電路的工作電壓為1.8V,操作溫
    度範圍為0℃ ~ 75℃,鎖相迴路的輸入參考頻率範圍為5MHz~10MHz,輸出頻率範圍鎖定
    在80MHz~160MHz,鎖定時輸出時脈抖動量為19.2ps~18.1ps (pk-pk)。鎖定時間在
    51.5us~49.1us,其消耗功率為 1.86mW~3.29mW。
    ;In recent years the performance and speed of VLSI circuits grew up with
    scale-down process, and now the chip changes to integrate SOC. There is often
    phase error or clock skew which generate asynchronous phenomenon in
    different sub-circuit blocks. The different phase of operate clock that
    caused to output data error in integrate system. Hence, it needs Phase-Locked Loop
    (PLL) for decreasing phase error that make the clock phase is corresponding
    in order to decrease output data error in sub-circuit of integrate system.
    The key point is to decrease the jitter of PLL output signal. The high linearity
    of Voltage-controlled Oscillator(VCO) achieves the goal.
    In this thesis, a wide band PLL with a high linearity voltage-controlled
    oscillator(HLVCO) in full range is proposed. How to achieve a HLVCO ? A idea is
    the beginning. Then validate the correctness of the HLVCO characteristics:
    f=KvcoVctrl+fmin by theoretic derivation. The key point is the performance of
    VCO bias circuit in the overall develop process. That is the relations of input
    voltage Vctrl and output current Ictrl of VCO bias have to be linear. In this
    thesis, four bias architectures achieving linear requirement are presented. First
    choose a best one from analyzing their advantages and drawbacks. Then from the
    process of design, simulation to validate the best one posses good features of
    full range operation, wide band and wide voltage. In the basis a multi-band HLVCO
    in full range operation is constructed. Finally a PLL is developed in this thesis.
    It produces five low jitter output phases achieving the goal of low output jitter
    mentioned previously. In the different process corners and temperatures the
    frequency range of 80MHz~160MHz is locked correctly.
    We use the CIC CMOS 0.18um 1P6M virtual process with supplying 1.8V voltage
    in proposed PLL. The temperature range is 0℃ ~ 75℃. The reference input frequency
    range is 5MHz~10MHz and the output frequency range is 80MHz~160MHz. The jitter
    of output frequency is 19.2ps~18.1ps (pk-pk). The lock time is 51.5us~49.1us and
    the power consumption is 1.86mW~3.29mW.
    Appears in Collections:[電機工程學系碩士在職專班] 博碩士論文

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