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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/68791


    Title: 基於K最佳演算法之可結構化天線組態且具軟性輸出的多輸入多輸出偵測器設計;Design of Antenna-Configurable MIMO Detector with Soft-output Based on K-best Algorithm
    Authors: 王聖弼;Wang,Sheng-pi
    Contributors: 電機工程學系
    Keywords: 多輸入多輸出偵測器;K最佳演算法;軟性輸出;MIMO detector;K-best;soft-output
    Date: 2015-07-21
    Issue Date: 2015-09-23 14:27:38 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 本論文研究著重在提出改良型K最佳演算法來降低傳統K最佳演算法的複雜度,並加入位元對數相似比值(Bit level Log Likelihood Ratio ,LLR)使效能位元錯誤率提升之軟性解調多輸入多輸出偵測器。此設計可適用於2x2、3x3、4x4、5x5和6x6不同天線組態,並支援64-QAM、16-QAM、QPSK和BPSK不同的調變方法。我們設計改良型K最佳演算法以取代傳統K最佳演算法每一層都需排序,改為兩層排序一次減少排序次數。同時提出編碼式列舉法(Code-Book Enumeration, CBE)來避免硬體使用除法並預測可能的展開子點,排序部分則設計平行切割合併法(Parallel-Slice Merge Algorithm, PSMA)和平行氣泡切割排序法(Parallel Bubble-Slice Sort, PBSS)來減少運算週期 ,加快硬體運算速度。除此之外,提出了一個有效率產生多組額外路徑的辦法,使效能有效提升。在硬體實現上,我們採用了管線式架構來設計以提高硬體操作頻率增加產出量,並利用折疊(Folding)架構有效利用硬體面積。在複雜度比較上,與傳統K最佳演算法比能減少最多46%的拜訪點數與最多62%乘法運算次數,有效降低演算法複雜度。最後硬體實現方面使用SMIMS VeriEnterprise Xilinx FPGA驗證電路功能。;In this thesis, we proposed modified K-best algorithm (MKB) to saving complexity from conventional K-best algorithm, and introduce the Bit level Log Likelihood Ratio (LLR) to complete MIMO detector with soft-output. It can support multiple antenna types (6×6, 5×5, 4×4, 3×3, 2×2), and various modulation schemes (64-QAM, 16-QAM, QPSK, BPSK) in this design. We replaced conventional K-best algorithm which sorting every layer with modified K-best algorithm which sorting two layers once to reduce half times of sorting. We also proposed Code-Book Enumeration (CBE) to avoid using divider and predict probable expand nodes. In order to reduce operation cycles, we design Parallel-Slice Merge Algorithm (PSMA) and Parallel Bubble-Slice Sort (PBSS) to improve hardware throughput. In addition, we proposed an algorithm that uses the information of K-Best signals in each layer of tree search and generate additional tree search paths to further enhance BER performance of the soft-output MIMO detector. We used pipeline architecture to increase operation frequency and use folding architecture to let hardware using efficiency in hardware implementation. From complexity comparison with conventional K-best algorithm, the proposed algorithm reduces visited node up to 46% and reduces the number of multiplications up to 62%. Finally, the proposed configurable MIMO detector with soft-output is verified by the SIMIS VeriEnterprise Xilinx FPGA development board.
    Appears in Collections:[電機工程研究所] 博碩士論文

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