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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/68975

    Title: 具抑制交互穩壓效應與強化輸出驅動能力之單電感雙輸出降壓轉換器;Single – Inductor Dual – Output Buck Converter with Cross – Regulation Reduction and Enhanced Output Driving Capability
    Authors: 黃子亘;Huang,Zi-Xuan
    Contributors: 電機工程學系
    Keywords: 單電感雙輸出降壓轉換器;交互穩壓效應;自適應路徑選擇器;輸出電流補償器;Single-inductor dual-output (SIDO) buck converter;Cross-Regulation;adaptive path selector;output current compensator
    Date: 2015-08-21
    Issue Date: 2015-09-23 14:49:05 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 本論文提出一個輸入電壓 3.3 V、輸出電壓 1 V 與 1.2 V、具抑制交互穩壓效應與強化輸出驅動能力之單電感雙輸出降壓轉換器。本設計使用分時多工控制,並操作在連續導通模式,這使得電路在系統分析上能更加的直觀,且能承受較大的輸出電流負載。而為了改善單電感雙輸出轉換器最常會被討論的交互穩壓效應,本論文提出了 自適應的路徑選擇器以及輸出電流補償器,藉由偵測輸出電壓漣波以及電壓位準,電路即可判斷出兩輸出端的負載大小並分配電感電流給予兩輸出端,若其中有輸出因為電流不足而產生壓降時,輸出電流補償器就會為其補充所需電流,藉此改善交互穩壓效應的產生。
    本論文之單電感雙輸出降壓轉換器使用 180 nm 3.3 V CMOS製程實現晶片。輸入電壓為 3.3 V,擁有兩個電壓輸出 1 V 與 1.2 V,操作頻率為 1 MHz,其中透過輸出電流補償機制,電路的交互穩壓效應改善量最低可達 65.3 %,而兩輸出端各自的供應負載電流範圍為 50 mA ~ 150 mA,晶片量測效率78.5 %,負載調節度 0.75 mV/mA,晶片面積則是 1.94 mm2。
    ;A single – inductor dual – output ( SIDO ) buck converter with Cross – Regulation Reduction and Enhanced Output Driving Capability has been presented in this thesis, which provides two voltage outputs 1 V and 1.2 V under 3.3 V supply voltage. Time – multiplexing control in continuous conduction mode has been used in this design, as a result, this circuit can be simpler for system analysis and support larger load current. To improve the cross – regulation, which has been discussed often in the SIDO converters, adaptive path selector and output current compensator have been proposed in this thesis. By sensing the output voltage ripple and voltage level, the circuit can compare the load current of the two outputs, and distribute inductor current for the outputs. When a voltage drop has occurred at the one of the output, which causes by insufficient output current, the output current compensator will compensate it. This method can improve the cross – regulation efficiently.
    The proposed SIDO buck converter has been fabricated in 180nm 3.3 V CMOS process, with two voltage outputs 1 V and 1.2 V under 3.3 V supply voltage at 1 MHz operating frequency. By the output current compensation, the cross – regulation improvement of the circuit can achieve 65.3 %. The load current range of the each output is 50 mA to 150 mA. The efficiency and the load regulation of the chip are 78.5 % and 0.75 mV/mA. The chip area is 1.94 mm2.
    Appears in Collections:[電機工程研究所] 博碩士論文

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