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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/69216

    Title: LTE上行鏈路發射機與接收機之FPGA 實現;Design and Implementation of LTE Uplink Transceiver with FPGA
    Authors: 黃君豪;Huang,Jyun-Hao
    Contributors: 通訊工程學系
    Keywords: 長期演進技術;可程式化邏輯閘陣列;單載波分頻多址;LTE;FPGA;SC-FDMA
    Date: 2015-10-20
    Issue Date: 2015-11-04 17:49:35 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 長期演進技術(Long Term Evolution, LTE)為第四代行動通訊重要技術之一,此技術之上行鏈路為單載波頻分多址(Single-Carrier Frequency Division Multiple Access, SC-FDMA)系統,基本架構相同於(Orthogonal Frequency Division Multiplexing, OFDM),SC-FDMA 是OFDM 先經由預編碼運算,此運算是經由離散傅立葉轉換(Discrete Fourier Transform, DFT)完成,使用預前編碼可降低均峰比(Peak-to-Average Power Ratio, PAPR),有效降低功率使用而降低製造成本。

    此篇論文將利用可程式化邏輯閘陣列(Field-Programmable Gate Array, FPGA)板實現,實現符合LTE 上行鏈路規格之發射機與接收機。在發射機之訊號處理模組中設計了串列轉並列處理器、星座圖映射器、DFT 處理器、IFFT 處理器、循環字首置入器和領航碼置入器等,而在接收機設計了訊號同步器、FFT 處理器、通道估測器、通道等化器、IDFT 處理器等。;LTE (Long Term Evolution) is important for fourth generation of mobile communication technologies. On the uplink transmission, the LTE system uses SC-FDMA (Single-Carrier Frequency Division Multiple Access) technology, is a technique essentially the same structure as OFDMA (Orthogonal Frequency Division Multiple Access). SC-FDMA pre-codes its information-bearing symbols by DFT (Discrete Fourier Transform). This pre-coding operation can reduce PAPR and can benefit power efficiency and reduce manufacturing cost.

    In this thesis, we conduct design and implementation of LTE uplink transceiver with FPGA (Field-programmable Gate Array). The transmitter includes parallel-to-serial module, constellation mapper, DFT, Invers FFT, cyclic prefix inserter and pilot inserter. The receiver includes signal synchronizer, FFT, channel estimator, channel equalizer, Invers DFT etc.
    Appears in Collections:[通訊工程研究所] 博碩士論文

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