形態學影像處理硬體加速器設計與應用;Design and Application of Morphological Image Processing Hardware Accelerator

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Title:	形態學影像處理硬體加速器設計與應用;Design and Application of Morphological Image Processing Hardware Accelerator
Authors:	羅鳴雁;Luo,Ming-yan
Contributors:	資訊工程學系
Keywords:	形態學;影像處理;硬體加速器;Morphological Image Processing;Hardware Accelerator
Date:	2015-12-21
Issue Date:	2016-01-05 18:27:14 (UTC+8)
Publisher:	國立中央大學
Abstract:	大多數形態學研究都強調硬體加速器，一旦需求改變或設計變更時，須重新設計硬體架構。本論文以MIAT(本實驗室)系統方法論，設計一個高彈性、可程式化的形態學影像處理硬體加速器架構。此架構包含多個串連的形態學核心模組(Mathematical Morphology Function Block, MMFB)，以管線化控制提升各模組的效能。藉由軟體控制其硬體表現行為，達到高度彈性化且通用性之硬體加速器。在功能驗證中以條碼辨識為例，使用本硬體架構將影像侵蝕，刪除不必要之資訊，在使用膨脹運算還原回原始影像資料，最後經辨識得到其結果。本研究的貢獻在於軟硬體整合，以軟體控制其硬體表現行為，且經功能驗證後，其硬體架構可提供高彈性化及通用性。;Most researches put emphasis on the hardware accelerator for mathematical morphology. If there is something wrong, the architecture will need to be redesigned. In this paper, MIAT (our laboratory) system methodology is used to design a high flexible and programmable morphological hardware accelerator. There are several morphology models (Mathematical Morphology Function Block) inside and pipeline control is used to improve each MMFB’s efficacy. We use software to control its hardware performance. By these means, it can achieve high flexibility and general purpose. We use barcode identification to verify this architecture. Noise is deleted with erosion operator and the origin image information is got by dilation. Finally, get the result with identification. The contribution of this paper is to integrate hardware and software. Control the hardware performance behavior with software. After functional verification, the hardware architecture provides high elasticity and general purpose.
Appears in Collections:	[Graduate Institute of Computer Science and Information Engineering] Electronic Thesis & Dissertation

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