編織演算法應用於自動化產生ADC實體電容陣列;Weave placement for auto generation physical capacitor array layout on ADC

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > Electronic Thesis & Dissertation > Item 987654321/70353

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/70353

Title:	編織演算法應用於自動化產生ADC實體電容陣列;Weave placement for auto generation physical capacitor array layout on ADC
Authors:	王俞鈞,;Wang,Yu-jin
Contributors:	電機工程學系
Keywords:	編織演算法;Weave algorithm
Date:	2016-05-06
Issue Date:	2016-06-04 12:54:57 (UTC+8)
Publisher:	國立中央大學
Abstract:	佈局的自動化設計在類比電路上可以大幅的降低設計時的高錯誤率、高複雜度的佈局操作所花費的時間與繁瑣的任務和昂貴的設計成本。由於敏感的寄生電容效應、元件的不匹配、製程變動與梯度效應都將導致佈局結果可能是一個不好的佈局，也造成了產品的不準確性與良率的降低。多數類比電路像是類比數位/數位類比轉換器或濾波器等等，其性能都依賴於準確的電容比值。對於要求準確的電容比值大都會使用多顆單位電容並聯取代單一顆大電容並考慮繞線引起的寄生效應，以減少一些不匹配的影響。本論文題出自動化電容排列演算法產生類比/數位轉換器的電容元件，遵守共質心法四項準則，讓陣列中元件可以達到分散、對稱、質心重疊、最密陣列，在以直方圖式的方法來評估模擬INL/DNL，並且將演算法以及評量器整合成一個使用者工具，讓使用者可以直接在陣列上輸入原件就可以快速評估也能手動微調原件位子確保電容比例的準確度 ;Automated layout design on analog circuits can significantly reduce the high error rate of the design, the time complexity of the layout of the high cost of operation and tedious task and expensive design costs.Due to the mismatch sensitive parasitic capacitance effects, components, process variation and gradient effect will lead to the layout result can be a bad layout, also caused inaccuracies and lower product yield.Most of analog circuits such as analog-digital / digital-to-analog converters or filters, etc., and its performance is dependent on accurate capacitance ratio.For most of the requirements of the exact capacitance ratio of the capacitor in parallel using multiple satellites units substituted single and considering a large parasitic capacitance caused by winding, in order to reduce some of the effects of the mismatch. This paper propose automatic placement algorithm for analog/digital capacitor device,it follow rule of common-centroid, making the array dispersion, symmetry, coincident and compactness, we use diagram method to test linearity and integrate algorithm with metric intoa user tool, user can quickly input placement in tool and simulate the result and also do detail change make sure the accurate of capacitor ratio.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

Files in This Item:

File	Description	Size	Format
index.html		0Kb	HTML	453	View/Open

社群 sharing

Loading...