晶圓級封裝重佈線路製程光阻殘留之研究;The Research of Photoresist Residue of Wafer Level Chip Scale Package Redistribution Layer Process

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/71564

Title:	晶圓級封裝重佈線路製程光阻殘留之研究;The Research of Photoresist Residue of Wafer Level Chip Scale Package Redistribution Layer Process
Authors:	劉振坤;Liu,Chen-Kun
Contributors:	光電科學與工程學系
Keywords:	光阻殘留;曝光強度;照射時間;曝光方式;鈍化層粗糙度;photoresist residue;exposure intensity;exposure time;exposure mode;passivation layer roughness
Date:	2016-08-02
Issue Date:	2016-10-13 13:17:23 (UTC+8)
Publisher:	國立中央大學
Abstract:	近年來電子產品隨摩爾定律，電子產品的功能及執行速度不斷提升及走向輕薄設計，以目前智慧型手機為例，除單純的輕薄設計外，鏡頭的畫素要求也愈來愈高，故半導體封裝的尺寸要求愈來愈小，且執行速度要求愈來愈快的狀況下，封裝製程容易因線路設計愈來愈密集而導致缺陷容易發生，因此考慮到製程良率及產品成本的狀況下，進行製程缺陷改善是必然的方向。本論文第二章及第三章，針對晶圓級封裝重佈線路曝光製程光阻殘留的問題，討論發生的理論機制。主要以重佈線路曝光製程的曝光強度、曝光照射時間、曝光方式及鈍化層粗糙度等方向，並利用田口分析法針找出最佳控制因子，解決光阻殘留問題。本論文第四章，探討重佈線路曝光製程光阻殘留原因，來自於使用不當的曝光強度及曝光照射時間過長，造成晶粒與晶粒之間反射光源過強，影響重佈線路曝光製程光阻殘留比例，減少曝光過程中光罩與晶圓接觸距離，以及鈍化層粗糙度增加，避免光源因漫射而造成之反射光源，以上兩種條件皆可有效降低光阻殘留。應用田口分析法找出曝光UV照射強度4mw/cm2，曝光照射時間65sec及曝光時光罩與晶圓距離為0㎛可得到最佳化參數設計。 ;In recent years , according to Moore’s law, the electronic related products have been promoted on function and execution speed concepts and trend to light and thin design. A case study of smart phone, it is not only light and thin design, but also high pixel. So semi-conductor under the package size getting smaller and execution speed become faster, package process become lead design closer to induce defect occurrence. Therefore, consider process yield and products cost, defect improvement is needed. In this thesis second chapter and chapter third, focus on Wafer Level Chip Scale Package Redistribution layers exposure process photo resistance residue problems, discuss the theoretical mechanisms occurrence. Mainly by the RDL exposure intensity, exposure time, exposure method, passivation layer roughness and use Taguchi methods to find out the optimized conditions to solve PR residue problems. The fourth chapter, discuss RDL exposure process photoresist residue problems occurs from unsuitable exposure intensity and long exposure time, induce high reflection light between chip and chip. Hence, impact RDL exposure process PR residue ratio. To reduce exposure distance between mask and wafer and rise passivation layer roughness, both conditions could avoid diffusion to induce reflection light effectively. Taguchi method result: exposure intensity 4mw/cm2, exposure time 65sec, soft contact is the optimized condition.
Appears in Collections:	[Graduate Institute of Optics and Photonics] Electronic Thesis & Dissertation

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