三維集成電路的發展與挑戰;The Development and Challenges of 3D IC

NCUIR > Engineering College > Graduate Institute of Mechanical Engineering > Electronic Thesis & Dissertation > Item 987654321/72359

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/72359

Title:	三維集成電路的發展與挑戰;The Development and Challenges of 3D IC
Authors:	李牧民;Lee,Mu-Ming
Contributors:	機械工程學系
Keywords:	三維集成;三維集成封裝;三維集成電路;矽穿孔;中介層;3D integration;3D IC packing;3D IC;Through Silicon Via;TSV;Interposer
Date:	2016-07-01
Issue Date:	2016-10-13 14:49:40 (UTC+8)
Publisher:	國立中央大學
Abstract:	本論文呈現的是一個針對三維集成，包含三維集成封裝、三維集成電路，以及使用矽穿孔技術的三維集成電路之深入探討研究報告。三維集成、封裝、三維集成電路以及矽穿孔等將在本研究中被定義，二維集成電路到三維集成電路的演化過程將被詳細說明，而整個三維集成電路和矽穿孔技術的架構和製程過程也都將在此論文中詳細呈現。本論文也將針對三維集成電路最重要核心結構的中介層做出詳細定義，也將針對中介層的完整製程流程做說明。最後，三維集成電路之檢測機制，應用範圍以及三維集成電路所將面臨之挑戰也被討論。 ;This thesis presents a survey of 3D integration, including 3D IC packing, 3D IC integration and also a survey of 3D Integrated Circuits using Through Silicon Vias (TSV). 3D integration, packing, 3D IC Integrated Circuits and also TSV will be defined, the evolution of 2D IC’s to 3D IC’s and the rationale for moving to these systems will be given, and a whole overview of the construction and process of the 3D Integrated Circuit and TSV will be presented. This thesis also will give a detail caption about the interposer, which is the heart of 3D IC, and also the manufacturing process of the interposer. Lastly, the testing mechanism, application and challenges of 3D Integrated Circuits using TSVs will be discussed.
Appears in Collections:	[Graduate Institute of Mechanical Engineering] Electronic Thesis & Dissertation

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