適用於合成孔徑雷達訊號壓縮之可適性區塊量化器設計;Design of Block Adaptive Quantizer for Synthetic Aperture Radar Signal Compression

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题名:	適用於合成孔徑雷達訊號壓縮之可適性區塊量化器設計;Design of Block Adaptive Quantizer for Synthetic Aperture Radar Signal Compression
作者:	蔡譽良;Tsai, Yu-Liang
贡献者:	電機工程學系
关键词:	可適性區塊量化器
日期:	2017-07-27
上传时间:	2017-10-27 16:12:07 (UTC+8)
出版者:	國立中央大學
摘要:	由於影像解析度提升造成影像資料量增加，衛星與基地站之間的傳輸通道容量有限，本論文為了有效地降低合成孔徑雷達衛星的影像資料並保持良好的影像解析度，設計了可適性區塊量化器(Block Adaptive Quantizer, BAQ)來壓縮合成孔徑雷達的回波訊號，在量化系統中，訊號來源分為In-phase(I) 軸與Quadrature(Q) 軸，將兩軸的輸入訊號切割成不同區塊，並利用各區塊所擁有的平均能量，來選擇Lloyd-Max量化器的量化邊界值(Threshold)與量化代表值(Representative)進而得到最小的量化均方誤差(Mean Square Error, MSE)，並使用MSE的數值配合著輸入訊號能量，計算出信噪比(Signal-to-Noise Ratio, SNR)來評估系統性能。在我們的BAQ系統中，可將ADC所輸入的訊號由8、10、12、14 bits壓縮成2、3、4、6或8 bits輸出，區塊大小可設定為128、256或是512，而變異數值切割有兩種模式，分別將變異數值區間平均分割成128與256等分。在硬體設計上，原先用來儲存量化標準的記憶體在所需支援的輸出字元長度下太過龐大，我們進行了架構的改良，透過變異數增幅的設計，每個輸出位元數只需儲存一組量化邊界值，同時再搭配一儲存變異數增幅數值的記憶體，使得記憶體使用量大幅下降了百分之九十九以上。在比較器的部分我們混合了序向比較與平行比較的方式，來取代原先的比較器設計，可有效降低使用到的加減法器個數。最後，使用Virtex-7系列的FPGA進行硬體設計驗證，為了追求更高的操作頻率，藉由平行處理及管線化(Pipeline)，操作頻率可達到500MHz左右，另一方面也使用了台積電所提供的40奈米製程進行實作，系統能操作在800MHz，而此系統功耗為11.8mW，由此可發現此系統有不錯的硬體使用效率。 ;The resolution requirements of remote sensing images become higher and the channel capacity from satellites to the ground stations is limited. In order to effectively reduce the image data of synthetic aperture radar and maintain good image resolution, a block adaptive quantizer (BAQ) is needed to compress the echo signals. In the BAQ, the input signals of the in-phase (I) and quadrature (Q) axes are divided into blocks. The statistics of each block such as the average energy is calculated to derive the parameters of Lloyd-Max quantizer including the thresholds and the representatives of each quantized region. The Lloyd-Max quantizer achieves the smallest mean square error (MSE) of the Gaussian distributed signals. The signal-to-noise ratio (SNR) based on the average energy of the input signals and the MSE of the quantized output is then evaluated. In our BAQ system, it can compress the ADC signals of 8,10,12,14 bits into 2, 3, 4, 6 or 8 bits outputs. The block size can be set as 128, 256 or 512 complex samples, and the whole possible variance range can be divided equally into either 128 or 256 segments depending on the user requirements. When the BAQ output wordlength is large, the memory for storing the Lloyd-Max quantizer thresholds is huge. Thus, we propose to use variance scaling technique to normalize the input signal energy. In this case, only one set of thresholds is needed with an extra memory for storage of variance scaling values. Over 98% memory sizes can be saved. In order to get the output of non-uniform Lloyd-Max quantizer, a hybrid comparator architecture is designed. The number of adders and subtracters is also reduced. The hardware is first realized by the FPGA of Virtex-7 series. To achieve a higher operating frequency, parallel processing and pipeline techniques are used. The operating frequency can reach 500MHz. The design is also implemented in 40nm CMOS technology and the operating frequency achieves up to 800MHz with power consumption of 11.8mW. Thus, our design has good hardware efficiency and low power consumption.
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