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    請使用永久網址來引用或連結此文件: http://ir.lib.ncu.edu.tw/handle/987654321/74998


    題名: K頻段互補式金氧半場效電晶體低功耗低相位雜訊四相位時脈產生器之研製;Design of K-band CMOS Low Power Low Phase Noise Quadrature Clock Generator
    作者: 沈毅恩;Shen, Ian
    貢獻者: 電機工程學系
    關鍵詞: K頻段;注入鎖定;壓控振盪器;四相位;互補式金氧半場效電晶體;鎖頻迴路;低相位雜訊;K-band;Injection locking;Voltage-Control-Oscillator;Quadrature;CMOS;Frequency-Locked-Loop;Low phase Noise
    日期: 2017-09-29
    上傳時間: 2017-10-27 16:15:22 (UTC+8)
    出版者: 國立中央大學
    摘要: 在射頻收發系統中,本地振盪源扮演極重要的腳色,又為了因應高速資料傳輸量的需求,使得本地振盪源需要操作在較高頻率,如何產生一個低功耗、低相位雜訊且低抖動量的本地振盪源,在現代通訊系統中是值得研究的。而四相位本地振盪源可以應用於抑制鏡像訊號,以及通訊系統的調變、解調變。本論文主要針對K頻段的四相位本地振盪源,以達到低功耗、低相位雜訊及低抖動量之研究。第二章闡述一個K頻段自我注入耦合四相位壓控振盪器之電路分析、設計及量測結果。第三章闡述一個K頻段變壓器耦合式次諧波注入鎖定四相位壓控振盪器之電路分析、設計以及量測結果。第四章則為不同模態的訊號源分析比較及具鎖頻迴路自對準之次諧波注入鎖定四相位壓控振盪器之電路設計與量測結果。本論文的設計均採用台積電提供的90奈米互補式金氧半場效電晶體製程(TSMC 90 nm GUTM CMOS)。
    第二章介紹數種四相位振盪器的耦合架構及設計原理,並且提出自我注入耦合的方法,並使用電流再利用及變壓器回授的方法降低相位雜訊,且使用位元控制器來增加振盪器的可調頻寬,同時實現一個K頻段自我注入耦合四相位壓控振盪器,量測頻率為18.1到21.4 GHz,可調頻寬為3.3 GHz相當於16.7%比例頻寬,距載波偏移1 MHz的相位雜訊為-109 dBc/Hz,相位誤差及振幅誤差分別為0.28°及0.13dB,電路直流總功耗為8.4 mW。
    第三章介紹注入鎖定及倍頻器的架構及設計原理,並且提出變壓器耦合式的注入鎖定的方法,並使用電流再利用的方法降低直流功耗,且使用自我注入耦合的方式產生四相位訊號,同時實現一個K頻段變壓器耦合式次諧波注入鎖定四相位壓控振盪器,輸出頻率從22.9到25 GHz,可調範圍大約為2.1 GHz,以十六分之一訊號注入後,鎖定頻寬約為200MHz,在距載波偏移1 MHz的相位雜訊為-120.7 dBc/Hz,抖動量積分範圍由1 kHz到40 MHz為37.1 fs。最小四相位誤差及振幅誤差分別為0.02°及0.35 dB,電路直流總功耗為7.2 mW。
    第四章為具鎖頻迴路自對準之次諧波注入鎖定四相位振盪器。首先介紹理論模型及轉移函數,接著利用ADS(advance design system)軟體進行模擬分析鎖頻迴路以及各種不同的頻率合成器架構的相位雜訊及抖動量,量測的鎖頻範圍為22.9到25GHz,各個控制電壓的鎖定範圍約為200 MHz,輸出功率大於-10 dBm。距載波偏移1 MHz的相位雜訊為-119.4 dBc/Hz,抖動量積分範圍由1 kHz到40 MHz為36.7 fs,最小四相位誤差及振幅誤差分別為0.44°及0.1 dB電路直流總功耗為40 mW,和過去文獻比較擁有最佳的優化指數(FOM)。
    ;In radio frequency (RF) transceiver circuit, local oscillator (LO) is an indispensable building block, since the demand for high data transmission rate is increasing, Design a high-frequency, low power, low phase noise and low jitters LO is an important issue.LO with quadrature outputs in RF transceiver is for the applications of image rejection and modulation/demodulation. This thesis focuses on K-band LO with quadrature outputs to achieve low power consumption, low phase noise and low jitters. Analysis, design and measured results for K-band quadrature voltage-controlled oscillator (QVCO) using self-injection coupled (SIC) topology are proposed in Chapter 2. Analysis and design of the K-band sub-harmonic injection-locked QVCO (SILQVCO) using transformer coupled (TC) topology are proposed in Chapter 3. Analysis, design and measured results for a K-band TC-SILQVCO with frequency-locked loop (FLL) self-alignment are proposed in Chapter 5. All of the designs in this thesis are fabricated using TSMC 90 nm GUTM CMOS process.
    Several topologies of QVCO are introduced in Chapter 2. The SIC-coupled, current reused and transformer feedback are investigated to obtain the design methodology. Also, the bit-controller is used to increase tunning range. The proposed K-band SIC-QVCO features a tunning range of 3.3 GHz and a 16.7% fractional bandwidth, the measured phase noise at 1 MHz offset is -109 dBc/Hz. The minimum quadrature phase and amplitude error are 0.28° and 0.13 dB respectively, and the DC power consumption is 8.4 mW.
    Several frequency multiplier and the injection-locked theory are introduced in Chapter 3. The transformer coupled approach is adopted in VCO design, and the proposed VCO using self-injection coupled technique can generate quadrature signal. TC-SILQVCO using current reused technique can be operated in lower DC power consumption. The measured locked range of the K-band TC-SILQVCO is from 22.9 to 25 GHz and locking range for each control voltage is about 200 MHz. The measured output power is higher than -10 dBm over the range. The measured phase noise (1 MHz offset) and RMS jitter (integrated from 1 kHz to 40 MHz) are -120.7 dBc/Hz and 37.1 fs, respectively. The minimum quadrature phase error and amplitude error are 0.02° and 0.35 dB, the total power consumption is 7.2 mW.
    In Chapter 5, we proposed a K-band TC-SILQVCO with frequency-locked loop (FLL) self-alignment. First, analysis of the FLL, including the theoretical models, transfer functions and models using ADS (advance design system) software with system setup of each blocks in FLL. A theoretical model of the SILFLL is proposed, and the calculated phase noise and jitter are presented for the comparison of various topologies frequency synthesizer. The measured locked range of the SILFLL is from 22.9 to 25 GHz, and the locking range for each control voltages is about 200 MHz. The measured output power is higher than -10 dBm over the range. The measured phase noise (1 MHz offset) and RMS jitter (integrated from 1 kHz to 40 MHz) are -119.4 dBc/Hz and 36.7 fs, respectively. The total DC power consumption is about 40 mW, and this work has the best FOM as compared with literatures.
    顯示於類別:[電機工程研究所] 博碩士論文

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