| 摘要: | 以矽為主體的積體電路科技依摩爾定律於過去50年間發展迅速，成為資訊時代發展之主要動力。然而僅靠元件尺寸的微縮已不足以解決積體電路在元件性能、功耗與製造成本上所面臨的問題。因此，在晶圓技術進入10奈米世代之後，尋找適當電晶體材料突破上述瓶頸已是當務之急。砷化銦(InAs)材料因具窄能隙與高電子遷移率的優點，於未來可應用於低操作電壓之N型通道材料，而銻化鎵(GaSb)則具備高電洞遷移率的優勢可應用於P型通道材料，砷化銦與銻化鎵是最符合低耗能高速邏輯電路的化合物半導體材料組合。然而，砷化銦與銻化鎵的金氧半(Metal-Oxide-Semiconductor)界面缺陷密度仍是影響金氧半場效電晶體性能的關鍵性問題。本研究的主旨為開發具有低界面缺陷能態密度之砷化銦與銻化鎵金氧半電容，研究內容囊括臨場式、非臨場式與氣體電漿表面處理製程技術，並研析這些製程技術對砷化銦與銻化鎵金氧半電容界面特性的影響。
為研發臨場式金氧半電容製作技術，此研究所使用的分子束磊晶系統與原子層沉積系統是以一超高真空傳輸腔體連接，以避免磊晶片暴露大氣產生原生氧化物，而對金氧半界面造成影響。藉由分子束磊晶技術可控制磊晶片表面原子重建狀態，經超高真空傳輸腔體可維持表面原子排序狀況下傳送至原子層沉積系統。經過有系統地調整磊晶參數與表面原子狀態，以臨場式製作的氧化鉿/砷化銦金氧半電容經電導法計算之中間能帶界面缺陷能態密度為2.12 × 10E12 cm-2eV-1；用臨場式製作的氧化鉿/氧化鋁/銻化鎵金氧半電容之中間能帶界面缺陷能態密度為1.86 × 10E12 cm-2eV-1。以臨場式製程製作銻化鎵金氧半電容須特別注意表面重建狀態，因為過多銻原子堆積之表面狀態將導致氧化鉿三維島狀沉積，劣化元件之電性，本論文亦針對此現象提出其物理沉積模型。
臨場式製程技術雖具良好的氧半電容界面特性，為因應未來三維結構為主的鰭式、奈米層片狀或全包覆式金氧半場效電晶體製程趨勢，本研究亦探討非臨場式製程方法，如使用化學溶液處理磊晶片，再製作成金氧半電容。於砷化銦材料部份，經鹽酸處理的氧化鉿/氧化鋁/砷化銦電容之界面缺陷能態密度為1.3 × 10E12 cm-2eV-1在銻化鎵材料方面，用鹽酸處理的氧化鉿/氧化鋁/銻化鎵金氧半電容之界面缺陷能態密度為5.3 × 10E13 cm-2eV-1。
於非臨場式的研究結果得知，僅使用化學溶液進行化學處理的界面特性優化之成效有限，吾人提出一混合式界面處理法，即先使用化學溶液去除原生氧化層，再於電漿式原子層沉積系統進行表面電漿處理與高介電材料沉積。以鹽酸搭配氮氣電漿處理所製作的氧化鉿/氧化鋁/砷化銦電容之中間能帶界面缺陷能態密度可降至7.6 × 10E11 cm-2eV-1。此外，吾人發現氫氣電漿易使砷化銦材料表面產生銦原子簇集現象，而使用氮氣電漿則可使晶片表面產生氮化披覆層，有助於獲得較佳之表面狀態，本論文中對該物理現象亦提出一沉積模型說明之。在銻化鎵材料部份，吾人發現使用鹽酸結合氮氣電漿會使銻化鎵電容產生費米能階釘札現象而無法調控載子，於是本研究開發了階段式電漿處理製程技術，此技術為先以氫氣電漿處理而產生氧化鎵鈍化層後，再使用氮氣電漿進行氮化處理而產生氮氧化鎵界面層，以此法製作之氧化鉿/氧化鋁/銻化鎵電容之界面缺陷能態密度可達6.4 × 10E12 cm-2eV-1。
綜上所述，臨場式製程可降低砷化銦與銻化鎵金氧半電容之界面缺陷與解決費米能階釘札現象。在非臨場式狀況下，吾人結合化學溶液處理與原子層沉積系統電漿處理之混合式製程，可使砷化銦與銻化鎵電容維持低界面缺陷能態密度、低閘極漏電流、高電容調變率與高閘極電容值。此界面處理技術適用於常見之三維電晶體製程，極具實用性，未來將可應用於砷化銦與銻化鎵組合的低耗能邏輯電路。
;Over the last 50 years, Si-based complementary metal-oxide-semiconductor (CMOS) technology has advanced closely following Moore’s Laws, which has in turn facilitated the development of information technology era. However, device scaling of integrated circuits has encountered severe challenges in device performance, power consumption and manufacturing costs. Finding appropriate materials and technologies to solve these problems is the top priority in semiconductor industry. In this research, we study and fabricate low interface trap density (Dit) InAs and GaSb metal-oxide-semiconductor capacitors (MOSCAPs), and explore the possibility of using these two materials for next generation n- and p-channel three dimensional transistors. InAs is a narrow bandgap material having high electron mobility, which makes it suitable for low power n-channel transistors. GaSb, on the other hand, has high hole mobility and is a good candidate for low power p-channel devices. However, both InAs and GaSb suffer from high Dit at the oxide-semiconductor interface, which limits the modulation of carriers in the channel. In this study, we investigate three processes, including in-situ, ex-situ, and nitrogen/hydrogen plasma treatments for fabricating InAs and GaSb MOSCAPs, and correlate these treatments with the characteristics of the MOSCAPs.
To avoid the notorious native oxides, which sabotage the electrical characteristics of InAs and GaSb MOSCAPs, in-situ preparation of the samples are carried out by connecting the molecular beam epitaxy (MBE) system with the ALD system via an ultra-high vacuum (UHV) transfer tube. HfO2/InAs MOSCAPs prepared by this method exhibit a Dit of 2.21 × 10E12 cm-2eV-1 at the mid-gap as estimated by conductance method. As for GaSb MOSCAPs, devices fabricated on the Sb-stabilized (1 × 3) surface exhibit a Dit as low as 1.86 × 10E12 cm-2eV-1 near the mid-gap, while the devices fabricated on the Sb-rich (2 × 5) surface exhibit short-circuit behavior. This is attributed to the presence of excessive Sb clusters, which cause island growth during the deposition of dielectric films. A physical model is proposed to explain the mechanism.
Since three-dimensional transistors, such as fin field-effect transistors (FinFETs), nano-sheet transistors (NSTs), and gate-all-around (GAA) MOSFETs, are the mainstream devices, ex-situ processes for fabricating InAs and GaSb MOSCAPs have also been developed. Using chemical solution treatment, optimized trimethylaluminium (TMAl) surface treatment and post metal annealing (PMA) processes, Dit of 1.3 × 10E12 cm-2eV-1 is achieved on HfO2/Al2O3/InAs MOSCAPs and 5.3 × 10E13 cm-2eV-1 on GaSb MOSCAPs.
To further reduce the density of interface states, an ex-situ process consisting of HCl solution chemical treatment and nitrogen plasma treatment has been developed for fabricating HfO2/Al2O3/InAs MOSCAPs, which exhibit a Dit of 7.6 × 10E11 cm-2eV-1 near the mid-gap. The reduction of Dit is attributed to the formation of a nitride layer on the InAs surface. It is also found that hydrogen plasma is much more reactive than nitrogen plasma, and tends to induce indium clusters on InAs surface, resulting in high leakage current. For GaSb MOSCAPs, a sequential treatment by HCl chemical cleaning and nitrogen plasma surface treatment leads to Fermi level pinning at the oxide/GaSb surface. Using HCl chemical cleaning and hydrogen plasma treatment, however, there forms a layer of GaOx on the surface. Subsequent nitrogen plasma treatment then leads to the formation of a GaON layer. HfO2/Al2O3/GaSb MOSCAPs prepared by this sequential plasma treatment process show an Dit of 6.4 × 10E12 cm-2eV-1.
The aforementioned results demonstrate that low Dit and unpinned surface of InAs and GaSb MOSCAPs can be obtained by in-situ processes. Meanwhile, InAs and GaSb MOSCAPs with high capacitance, low leakage, low Dit, and high capacitance modulation can also be fabricated by using ex-situ processes, consisting of chemical solution treatment and plasma treatment in ALD system. These surface treatment techniques can be readily applied to the fabrication of future three dimensional transistors for low power consumption CMOS integrated circuits. |
