在IC設計過程中，測試製程是影響製造成本之主要原因，而現行之測試需要仰賴客戶額外分析測試數據來判斷製程狀況，會額外耗費許多時間，不能即時做出製程調整，所以本計畫規劃一年，將以深度學習技術來強化IC測試過程中之資料分析，透過收集IC電性參數與錯誤發生原因來開發深度學習模型，藉由神經網路訓練來擷取出錯誤原因與電性參數之相關性及特徵值，可在獲得測試之電性參數後，產生錯誤發生原因達到監控測試設備站的性能並識別異常值，可減少客戶分析資料之時間，提早做出判斷。並透過各種資料分析技術來優化測試流程，主要主要針對測試過程中小批量晶片之測試結果為輸入進行訓練，希望能獲取測試項目之相關性與測試結果之分布狀況特徵，依電性參數之測試結果分佈，挑選與其他晶片差異最小之樣本作為優品，同時利用深度學習模型所找出之測試結果中有高度相依性項目，透過減少這些項目來降低測試時間，將上述的方式整合於良品/不良品與優品的測試過程，優化測試流程，應用於後續整批晶片之測試，減少整體測試所需時間，降低測試成本。 ;In the IC design process, the test process is the main factor of production cost. Existing tests rely on additional analysis of testing result data by the customer to determine the status of the process, which could take an additional amount of time and cannot adjustment of the process immediately. The project uses deep learning algorithm to enhance data analyzing during IC testing. To develop deep learning models, we collecting IC’s electrical properties and the causes of errors, extracting the feature of IC’s electrical properties and the causes of errors after training the network. After obtaining the electrical parameters of the test, the network produce the reason error occurs to achieve monitoring the testing equipment, which could reducing time for customers to analyze data and makes early judgments. During the test process, the program uses deep learning algorithm to train the correlation of the test items and the distribution characteristics of the test results with the small batches of test results of wafers. According to the distribution of test results of electrical properties, the samples with the least difference from other wafers are selected as the excellent products. At the same time, use the deep learning model to find highly dependent data in the test results. By reducing these items, the test time could be reduced. The methods above are integrated into the testing process of good, bad and excellent products, can be used for testing of remaining wafer to reduce the time and the cost required by overall testing.
