在物聯網應用中，極低功率消耗是一關鍵要求。在系統晶片中，大部分的面積都是由內嵌式記憶 體元件所占據。同時，這些內嵌式記憶體的漏電流所產生的功率消耗佔整體晶片的功率消耗比 例，在製程尺寸越小時，所佔的比重越重。在系統待命時，若可以關掉記憶體之電源又不會造成 資料消失的話，可以節省巨大的靜態功率消耗進而達到極低功率消耗之目標。因此，許多新興非 揮發性隨機存取記憶體也被提出來，企圖取代現有快閃記憶體及部分動態隨機存取記憶體，以改 善系統性能及功率消耗。被供認最有可能之記憶體為電阻式非揮發性記憶體。然而，如何有效測 試這些採用新興元件之隨機存取記憶體是一大挑戰，因此本計畫將針對這些記憶體開發完整之測 試技術，包含錯誤模型建立、測試演算法開發、自我測試電路開發、及測試演算法自動產生、錯 誤涵蓋率模擬、與內建自我測試電路設計自動化平台之建立。 ;Low power consumption is one key requirement for the Internet of Thing (IoT) applications. In system-on-chips (SoCs), embedded memories represent a significant portion of chip area. Also, the ratio of the leakage power of those memories to the leakage power of the SoC is higher and higher with the scaling of transistor size. If we can turn off the supply voltage of embedded memories without losing the data when the system is in standby mode, the static power consumption can drastically be reduced such that the objective of low power consumption can be achieved. Therefore, many emerging non-volatile RAMs have been proposed to attempt to replace current flash memories and DRAMs for improving the power consumption and performance. Resistive nonvolatile memories have been acknowledged as good candidates. However, how to test those RAMs using emerging devices is one big challenge. Consequently, this project is to develop comprehensive testing techniques for resistive nonvolatile memories, including fault modeling, development of test algorithms, development of built-in self-test (BIST) circuits, and platform of test algorithm generation, fault coverage evaluation, and BIST design automation.
