為了解決系統驗證的問題，數位電路通常會採用FPGA來仿真(emulate)電路，藉由把設計轉化成硬體的方式，大幅加快模擬的速度；然而，類比電路尚無法透過類似FPGA的仿真機制來加速模擬的程序，只能靠SPICE這類的模擬工具慢慢分析，使得混合訊號系統的驗證變成了設計流程中很大的瓶頸。因此，在之前的計畫之中，我們提出採用波數位濾波器(WDF)的理論來仿真類比電路的方法，將連續訊號之類比電路對映至離散的數位等效電路，即可直接利用數位的仿真技術來仿真類比的電路，並能直接跟數位電路整合，一舉解決混合訊號系統整合與驗證的問題。 在這個類比仿真流程中，首先得開發一套方法，將類比電路的SPICE netlist轉換成對應的WDF netlist，而這部分的工作在之前的計畫中已經大致完成，然而，在完成WDF netlist之後，仍需要將整個WDF模型合成到FPGA之上，才能進行電路仿真。這部分的硬體實現流程大致上可分成定點表示法(fixed point)的轉換、架構的合成與最佳化、管道化設計與時序最佳化、以及FPGA的合成等四大步驟，雖然FPGA的合成與最佳化已經有很多文獻可以參考，但由於WDF的特性與其他的數位濾波器不盡相同，這些演算法還是必須進行相當的調整，才能產生出最佳的電路。因此，本計畫也將試著開發一系列的CAD工具，對此類比電路仿真器進行面積與速度的最佳化，以提升系統驗證的效率。若能成功開發出這樣的技術，相信可以大大地加速整個驗證的流程，早日解決混合訊號系統驗證的瓶頸。 ;For system verification, digital circuits can be verified by hardware emulation with Field-Programmable Logic Array (FPGA) to obtain significant simulation speedup. However, no similar emulation mechanism is available now for analog circuits to speed up the simulations. Users still have to spend a lot of SPICE simulation time on the verification for analog parts. It makes the verification of mixed-signal systems become a big bottleneck in the design flow. Therefore, in our previous project, we proposed to use the Wave Digital Filter (WDF) theorems on analog circuit emulation. Using this technique, the analog circuits can be emulated in digital environment through mapping the analog circuits with continuous signals into digital equivalent circuits with discrete signals. Because the analog circuit emulation and digital circuit emulation can be directly integrated in the same environment, the verification bottleneck of mixed-signal systems can be eliminated with this technique. In this analog emulation flow, the first step is to develop a method to automatically translate the analog circuit netlist into the corresponding WDF netlist. This step was mostly completed in our previous project. However, there is still one step to synthesize the WDF netlist into FPGA before starting circuit emulation. This hardware implementation step can be roughly divided into four parts: fixed-point transformation, synthesis and optimization of WDF structure, pipeline design and retiming, and FPGA implementation. Although there are a lot of works in the literature about FPGA synthesis and optimization, proper modifications are still required for those algorithms to generate optimal emulators because the WDF properties are different from those of traditional digital filters. Therefore, in this project, we will try to develop a series of CAD tools for the design and optimization of the synthesized WDF circuits to improve the efficiency of mixed-signal system verification. With these new techniques, this analog circuit emulation platform can certainly save considerable simulation time for analog circuits and eliminate the verification bottleneck of mixed-signal systems.
