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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/8118


    Title: 覆晶式Ka頻段接收機前端電路與分佈式寬頻放大器之研製;Implementation of the Ka Band Receiver Front-End Circuits with Flip-Chip Package Technology and Distributed Amplifier Design
    Authors: 李典錡;Dian-Chi Li
    Contributors: 通訊工程研究所
    Keywords: 接收機前端電路;低雜訊放大器;覆晶式;flip-chip;receiver front-end circuits;lna
    Date: 2005-07-09
    Issue Date: 2009-09-22 11:18:37 (UTC+8)
    Publisher: 國立中央大學圖書館
    Abstract: 隨著影音多媒體服務逐漸普及,因此網路頻寬需求日益增加。毫米波頻段系統提供了較寬的頻帶,滿足了現代通訊高速率與寬頻的需求,因而成為了無線寬頻通訊產品之重要技術,例如區域多點分佈服務系統(LMDS:Local Multipoint Distribution Service)。除了頻譜需求的考量之外,其獨特的優點特別適於高階的無線通訊產品之發展;諸如頻帶寬對載波頻段相對比例較小,因此較容易達到寬頻應用,同時由於其波長大小適中,許多被動元件與天線尺寸不致太小或太大,更加方便實現。接收機前端電路包含低雜訊放大器、寬頻低雜訊放大器以及分佈式寬頻放大器都是其中毫米波頻段接收機系統設計上的重要電路,這領域是一個非常具有發展性的研究主題。 本論文主要研究內容為射頻毫米波頻段前端電路設計,其包含Ka頻段與V頻段。所設計的晶片皆利用WIN 0.15mm pHEMT製程研製,並且將所設計的晶片應用覆晶式封裝技術期望探討其特性,以利未來開發整體接收端系統模組化。 所設計之晶片其量測與模擬結果如下,共平面波導28 GHz低雜訊放大器的增益為28.6 dB,輸入1 dB壓縮點為-15 dBm,雜訊指數為3.5dB;10-30GHz低雜訊放大器的增益為14.5 dB,輸出1 dB壓縮點功率為10 dBm,雜訊指數為6dB;共平面波導分佈式寬頻放大器在頻寬達32GHz內,增益為大於5 dB,輸出1 dB壓縮點功率為大於5 dBm。共平面波導達靈頓分佈式寬頻放大器在頻寬達35GHz內,增益為大於5 dB,輸出1 dB壓縮點功率為大於5 dBm。V頻段低雜訊放大器則增益模擬結果為18 dB,頻寬範圍為10GHz,雜訊指數為4.84 dB。 As the wireless multi-media services become more and more popular, therefore broadband wireless access techniques are developed to satisfy these demands. The millimeter wave system takes advantages in the wide frequency range, and matches the trend of high data rate and wide-bandwidth in modern wireless communication system. The millimeter wave system, such as LMDS (Local Multipoint Distribution Service), plays an important role in the wireless-broadband technologies. The receiver circuits include low noise amplifiers, broadband low noise amplifier, and distributed amplifier, which are the key components in LMDS system. The thesis focuses on the millimeter wave receiver front-end circuit designed, which include the low noise amplifiers in Ka band and V band. The circuits are implemented with WIN 0.15mm pHEMT technology, and then apply the filp-chip package technology to investigate the issues of high frequency interconnects. The integrated millimeter wave front end by flip-chip package will be developed in the next study phase. The measured and simulated results of the designed circuits are illustrated as followings; for the coplanar waveguide 28GHz LNA, the obtained gain is 28.6 dB, input power at the 1-dB gain compression point is -15 dBm, noise figure is 3.5 dB; for 10-30GHz wideband LNA, the gain is 14.5 dB, output power at the 1-dB gain compression point is 10 dBm, noise figure is 6dB; for the coplanar waveguide distributed amplifier, gain is more than 5 dB within 32GHz bandwidth, output power at the 1-dB gain compression point is more than 5 dBm; for the coplanar waveguide Darlington distributed amplifier, the gain is more than 5 dB in within 35GHz bandwidth, output power at the 1-dB gain impression point is more than 5 dBm. The V-band LNA has 18dB gain and the bandwidth is 10GHz, and noise figure is 4.84 dB.
    Appears in Collections:[通訊工程研究所] 博碩士論文

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