歐規的數位電視地面廣播系統(DVB-T)使用了正交分頻多工(OFDM)的技術，而快速傅立葉轉換(FFT)是實現整個DVB-T內接收機系統的一個重要關鍵，因此訊號即時的處理顯得相當重要。自從1965年Cooley-Tukey首先提出快速傅立葉轉換演算法後，許多類似的演算法也相繼被提出，其中Radix-22 就是其中之一。 本論文中，採用Radix-22 FFT演算法，並以管線化(Pipeline-based)為基礎之單一路徑延遲回授(SDF)硬體架構來實現整個快速傅立葉轉換處理器。架構中以座標軸數位旋轉計算器(CORDIC)取代複數乘法器，以降低硬體複雜度；而架構中所需用到之記憶需求量非常龐大，在此以FPGA內部記憶體(Block Memory)來實現，達成節省硬體資源之目的。最後透過Xilinx Virtex-II Pro XC2vP30-FF1152 FPGA來實現2048/8192點的快速傅立葉轉換電路，已驗證本論文所提之快速傅立葉轉換處理器架構。 The European standard for terrestrial digital video broadcasting (DVB-T) adopted the orthogonal frequency-division multiplexing (OFDM) technique. Fast Fourier Transform is a key point to implement a DVB-T inner receiver. Therefore, the signal processing immediately is very important. Many similar Fourier transform algorithms are proposed after the first proposed by Cooley-Tukey in 1965. Radix-22 algorithm is one of them. In this thesis, we implement a FFT processor which based on Single-Path Delay Feedback (SDF) of pipeline-based architecture. To decrease the hardware complexity, we use the Coordinate Rotation Digital Computer (CORDIC) in place of complex multiplexer. It needs a lot of memory in the architecture, so we implement it by Block Memory in FPGA to achieve the goal that saving hardware resources. At last, we implement the 2048/8192 points of FFT circuit on Xilinx Virtex-II Pro XC2vP30-FF1152 FPGA to verify the architecture that we proposed.
