數位電視內接收機同步系統之設計與實現; Design and Implementation of Synchronization System for DVB-T Receiver

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Title:	數位電視內接收機同步系統之設計與實現;Design and Implementation of Synchronization System for DVB-T Receiver
Authors:	黃富生;Fu-Sheng Huang
Contributors:	通訊工程研究所
Keywords:	同步;正交分頻多工;數位電視;DVB-T;OFDM;synchronization
Date:	2006-06-27
Issue Date:	2009-09-22 11:19:18 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	歐規的數位電視地面廣播(DVB-T)採用正交分頻多工(OFDM)的調變技術，此技術能在頻率選擇衰減通道下，提供高速率、高頻譜效率的數位傳輸與多媒體服務。然而，同步誤差對OFDM系統效能影響甚大，系統中需要同步的包括符元時間、載波頻率、取樣頻率三項，而其同步之動作主要依賴循環字首訊號重複之相關性以及已知的引示訊號(pilot)來進行。本論文將就非同步對系統的影響以及系統對同步誤差的忍受程度進行研究分析，再針對各項同步提出估測之方式，建立一DVB-T適用的接收機同步系統。並以Verilog語言撰寫所設計之系統，搭配ModelSim軟體以及FPGA訊號實錄平台進行模組功能的驗證，最終將於FPGA硬體上實現此同步系統。 The terrestrial digital video broadcasting (DVB-T) of European Standard has adopted the orthogonal frequency division multiplexing (OFDM) modulation technique, that offers a high-rate, high bandwidth-efficient digital transmission and multimedia services over frequency-selective fading channels. However, OFDM is very sensitive to synchronization errors, and the synchronization of OFDM includes symbol timing, carrier frequency offset (CFO) and sampling frequency offset (SFO). The synchronization scheme is mainly based on the correlation of cyclic prefix and the pilot signals. This thesis has studied the effect of synchronization errors on the system, proposed schemes for each synchronization, and presented a synchronization system for DVB-T receiver. To implement the synchronization system on FPGA hardware, this thesis includes coding the presented synchronization system with Verilog language and verifying the function of modules with ModelSim software and FPGA hardware platform.
Appears in Collections:	[Graduate Institute of Communication Engineering] Electronic Thesis & Dissertation

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