摘要 台灣數位電視系統係採用歐規地面數位電視系統(DVB-T)，其正交頻率多工技術(OFDM)，可在無線傳輸環境下有效抵抗多路徑干擾的影響。 本論文研究方向為實現地面數位電視系統內接收機(DVB-T inner receiver)之FPGA硬體實現，將針對2K模式，循環字首長度1/8、頻寬6MHz的DVB-T規格，來進行系統的模擬與設計。模擬方面包括利用CORDIC架構來設計數位降頻器以及利用費洛濾波器架構來設計再取樣器，此兩架構的濾波器參數的選定將對系統性能造成不同程度的影響，於MATLAB模擬分析後選定適當參數來設計硬體，最後將硬體設計下載至FPGA版做實錄訊號驗證。此外利用UART埠建立錄訊號平台，可將硬體訊號傳至電腦做驗證，提供一個方便除錯的環境。 Abstract The European standard for terrestrial digital video broadcasting (DVB-T) was adopted in Taiwan,which was the Orthogonal Frequency Division Multiplexing(OFDM) technique that can effectually combat multi-path effect in the wireless communication environment. The thesis is focused on implementation of DVB-T inner receiver with FPGA hardware.For system simulation and design,we choose 2k mode、cyclic prefix 1/8、bandwidth 6MHz DVB-T standard.The system performance is affected by the parameters including CORDIC stage、 filter order and coefficients.The hardware design is downloaded to the FPGA development board for real-time implementation. Additionally, we built signal recoder platform by UART port,which can return the hardware result to computer for function testing. It also provide us an environment that can ease the degugging process.
