English  |  正體中文  |  简体中文  |  Items with full text/Total items : 65275/65275 (100%)
Visitors : 20939022      Online Users : 540
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version


    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/8173


    Title: 適用於OFDM系統之可變長度快速傅立葉轉換處理器設計與實現;Design and Implementation of Variable-Length Fast Fourier Transform Processor in OFDM Systems
    Authors: 王品鈞;Ping-chun Wang
    Contributors: 通訊工程研究所
    Keywords: 快速傅立葉轉換;座標軸數位旋轉計算器;Fast Fourier Transform;OFDM;CORDIC
    Date: 2007-06-27
    Issue Date: 2009-09-22 11:20:06 (UTC+8)
    Publisher: 國立中央大學圖書館
    Abstract: 快速傅立葉轉換(FFT)處理器被廣泛使用於正交分頻多工(OFDM)系統,且在不同應用的正交分頻多工系統中,快速傅立葉轉換處理的點數也不同。本論文中,將設計與實現一個可變長度的快速傅立葉轉換處理器,能適用於不同規格的正交分頻多工系統,譬如ADSL、DAB、DVB-T/H等。此可變長度之快速傅立葉轉換處理器以Radix-22演算法為基礎且使用單一路徑延遲回授(SDF)之管線架構實現。另外,雙轉子因子(Twiddle factor)的乘法以座標軸數位旋轉計算器(CORDIC) 並結合設計新的雙轉子因子產生方式,取代複數乘法器。架構中所需用到之記憶體以FPGA內部記憶體(Block Memory)來實現,達成節省硬體資源之目的。另外,針對OFDM系統如DVB-T,對FFT做定點數模擬分析性能,以降低硬體複雜度。最後透過Xilinx Virtex-II Pro XC2vP30-FF1152 FPGA來實現可變長度快速傅立葉轉換處理器電路,已驗證本論文所提之快速傅立葉轉換處理器架構 Fast Fourier transform (FFT) processor has been widely used in OFDM system and the sizes of FFT operations is varied in different applications of OFDM system. In this thesis, we design and implement a variable-length FFT processor architecture suitable for different specifications of OFDM applications, such as asymmetric digital subscriber loop (ADSL), digital audio broadcasting (DAB) and digital video broadcasting-terrestrial/handheld (DVB-T/H), etc. The variable-length FFT processor base on a radix-22 algorithm and Single-Path Delay Feedback (SDF) of pipeline-based architecture. In addition, The twiddle factor multiplications use Coordinate Rotation Digital Computer (CORDIC) in place of complex multiplexer and design new twiddle factor generation method. It needs a lot of memory in the architecture, so we implement it by Block Memory in FPGA to achieve the goal that saving hardware resources. Finally, we implement a variable-length FFT processor with Xilinx Virtex-II Pro XC2vP30-FF1152 FPGA to verify the architecture that we proposed
    Appears in Collections:[通訊工程研究所] 博碩士論文

    Files in This Item:

    File SizeFormat
    0KbUnknown905View/Open


    All items in NCUIR are protected by copyright, with all rights reserved.

    社群 sharing

    ::: Copyright National Central University. | 國立中央大學圖書館版權所有 | 收藏本站 | 設為首頁 | 最佳瀏覽畫面: 1024*768 | 建站日期:8-24-2009 :::
    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - Feedback  - 隱私權政策聲明