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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/81911


    Title: 分析負電容堆疊式環繞閘極場效電晶體之特性及負電容鰭式場效電晶體之隨機電報雜訊;Performance Analysis of Stacked Gate-All-Around Negative Capacitance FETs and RTN Analysis of Negative Capacitance FinFETs
    Authors: 林子棠;Lin, Zih-Tang
    Contributors: 電機工程學系
    Keywords: 鐵電材料;負電容場效電晶體;奈米線場效電晶體;奈米片場效電晶體;鰭狀場效電晶體;陷阱電荷;隨機電報雜訊;Ferroelectric material;negative capacitance FET (NCFET);Gate-All-Around;Nanowire FET;Nanosheet FET;FinFET;Interface trap charge;Random Telegraph Noise (RTN)
    Date: 2019-09-26
    Issue Date: 2020-01-07 14:37:27 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 隨著人工智能(AI)和物聯網(IoT)等應用的發展,高性能元件和超低功耗系統更顯得重要,而降低電源電壓(Supply voltage)是實現較低靜態和動態功耗的方法之一。因此陡坡元件(Steep slope device)對於超低功耗系統應用是必要的,若想要具有更好的Ion/Ioff比率以及次臨界擺幅低於60mV/dec,負電容場效電晶體(Negative Capacitance Field Effect Transistor, NCFET)是很有機會的前瞻元件之一。
    本文利用TCAD軟體結合Landau-Khalanikov方程式,分析7奈米以下技術節點之先進元件在堆疊鐵電層後的電特性。在次5奈米技術節點,奈米線場效電晶體和奈米片場效電晶體是很有潛力的元件,奈米線場效電晶體和奈米片場效電晶體(Negative capacitance Nanowire/Nanosheet FETs)可利用堆疊技術,在不增加面積的情況下,提升元件導通電流。在此研究中,我們研究並分析堆疊不同層的負電容奈米線場效電晶體和負電容奈米片場效電晶體的特性,堆疊一層的負電容奈米線場效電晶體之電容匹配較堆疊三層的負電容奈米線場效電晶體優異,所以堆疊一層的負電容奈米線場效電晶體有比堆疊三層的負電容奈米線場效電晶體更低的次臨界擺幅。此外,堆疊一層的負電容奈米線場效電晶體之C¬MOS較堆疊一層的負電容奈米片場效電晶體大,使得堆疊一層的負電容奈米線場效電晶體比堆疊一層的負電容奈米片場效電晶體有更大的電壓增益(Av,max)。進一步討論,奈米片場效電晶體的載子遷移率較奈米線場效電晶體大,使奈米片場效電晶體的導通電流較奈米線場效電晶體大。但是由於負電容奈米線場效電晶體有更大的電壓增益,使負電容奈米線場效電晶體與負電容奈米片場效電晶體的導通電流差縮小。
    其次,由於元件尺寸不斷縮小,當通道面積小於1μm2時,可能會只有單一顆氧化層陷阱電荷存在於通道表面。陷阱電荷對載子的捕捉和發射會導致類似隨機電報訊號造成通道電流的離散調變。因此,我們模擬單陷阱電荷對負電容鰭式場效電晶體所造成的隨機電報雜訊(Random Telegraph Noise, RTN),並且與傳統的鰭式場效電晶體做比較。負電容鰭式場效電晶體有較好的抗隨機電報雜訊能力,以及較低的臨界電壓變異度。另外我們提出利用不同摻雜型態的基板,進一步增加元件抗隨機電報雜訊能力並改善其臨界電壓變異度。
    最後,我們將負電容鰭式場效電晶體運用於邏輯電路上(Inverter、NAND、MUX),並且分析操作電壓(Supply voltage)、表面陷阱電荷(Interface trap charge)、以及通道長度變異度(Gate length variation)對於延遲時間(Delay time)的影響。相較於傳統的鰭式場效電晶體,負電容鰭式場效電晶體因為有較大的導通電流,所以有較低的延遲時間。且負電容鰭式場效電晶體因汲極引起能障上升,所以在降低操作電壓時,負電容鰭式場效電晶體的導通電流下降較不明顯,因此負電容鰭式場效電晶體的延遲時間,在降低操作電壓時所受到的影響較小。另外,負電容鰭式場效電晶體等效上的氧化層厚度較薄,所以受到表面陷阱電荷的影響也比傳統的鰭式場效電晶體來的小。我們也比較傳統鰭式場效電晶體與負電容鰭式場效電晶體在三個邏輯電路的能量延遲積(Energy Delay Product),我們發現負電容鰭式場效電晶體可以操作在較低的供應電壓,並表現出較好的能量延遲積。
    ;With the development of applications such as artificial intelligence (AI) and Internet of Things (IoT), high-performance components and ultra-low-power systems become more important, and reducing the supply voltage is a way to achieve lower static and dynamic power consumption. However, lowering the supply voltage also reduces the on-current (Ion) of the semiconductor component. Therefore, the steep slope device is necessary for ultra-low power system applications. However, the traditional MOSFETs are limited by the Bozeman distribution at room temperature, and the subthreshold swing cannot be lower than 60mV/dec. Negative Capacitance Field Effect Transistor (NCFET) with better Ion/Ioff ratio is one of the most promising candidate for ultra-low power system.
    In this dissertation, the gate-all-around (GAA) stacked negative capacitance nanowire (NC-NW) and nanosheet (NC-NS) FETs are analyzed comprehensively for the first time. Compared with the 3-stacked (3S) NC-NW FET, 1-stacked (1S) NC-NW FET shows larger maximum internal voltage gain (Av,max) due to better capacitance matching, lower minimum subthreshold swing (SS), and larger Ion improvements over nanowire (NW) FET. As the vertically stacked number of NW FETs increases, the effective Ion per unit width decreases due to the increased series resistance. At low gate bias (Vg,ext = 0V to 0.16V), 1S NC-NW FET with larger MOS capacitance (CMOS) with positive ferroelectric capacitance (CFE > 0) shows lower Av (at low Vg,ext) than the 1S NC-NS FET. As gate voltage increases, 1S NC-NW FET enters the negative ferroelectric capacitance region (CFE < 0), and therefore 1S NC-NW FET exhibits higher Av,max than the 1S NCNS FET due to its larger CMOS. Besides, 1S NC-NW FET exhibits +90% Ion improvements over NW FET, and 1S NC-NS FET shows +44% Ion improvements over nanosheet (NS) FET. NW FET exhibits lower DIBL than NS FET due to its better electrostatic control, while NC-NW FET shows more significant negative DIBL than the NC-NS FET due to its larger Av difference between high and low drain bias. NS FET with higher mobility shows larger Ion than the NW FET. However, the Ion difference between NC-NS and NC-NW becomes smaller because NC-NW exhibits larger Av,max.
    Second, we investigate the impacts of single trap induced Random Telegraph Noise (RTN) on negative capacitance FinFET (NC-FinFET) with P-type and N-type substrates, respectively, compared to FinFET. The trap position dependent RTN amplitude (∆Ids/Ids) along the channel length and fin height directions are examined. Our results show that NC-FinFET exhibits smaller RTN amplitude than FinFET due to its smaller trap induced threshold voltage shift (ΔVT). Besides, for both NC-FinFET and FinFET, N-type substrate shows smaller RTN amplitude and RTN induced ΔVT variations than P-type substrate. In other words, RTN induced variations can be suppressed by substrate doping optimization for NC-FinFET and FinFET.
      We investigate the NC-FinFET logic circuits (Inverter, NAND, MUX) considering the impact of supply voltage, interface trap charge, and channel length variation on the delay time. NC-FinFET with higher Ion exhibits lower delay time than the conventional FinFET. The Ion of NC-FinFET slightly decreases when it operates at lower supply voltage, which leads to increasing of the delay time. In addition, NC-FinFET with thinner effective oxide thickness shows better immunity to the surface trap charge induced threshold voltage shift compared to the conventional FinFET. Our results show that the NC-FinFET has better performance in Energy Delay Product (EDP) compared to the conventional FinFET at low supply voltage.
    Appears in Collections:[電機工程研究所] 博碩士論文

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