English  |  正體中文  |  简体中文  |  Items with full text/Total items : 78111/78111 (100%)
Visitors : 30638392      Online Users : 169
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version

    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/8234

    Title: 使用階層化設計方法於2.4 GHz 整數型頻率合成器;Multi-Level Design Methodology for a 2.4 GHz Integer-N Frequency Synthesizer
    Authors: 梁任芝;Jen-Chih Liang
    Contributors: 通訊工程研究所碩士在職專班
    Keywords: 階層化;鎖相迴路;頻率合成器;VerilogA;Frequency Synthesizer;PLL
    Date: 2007-07-04
    Issue Date: 2009-09-22 11:21:40 (UTC+8)
    Publisher: 國立中央大學圖書館
    Abstract: 本論文係採用階層化的方法實現2.4 GHz 整數型頻率合成器,在Level_1 中使用純數學的行為模型來描述系統的行為,可以快速的得到鎖相迴路的模擬結果,而在Level_2 則使用具有行為模型之邏輯電路來設計實際電路,並取代 Level_1 中的純數學模型,使其更接近實際電路的功能,最後再Level_3 中採用TSMC 0.18-µm CMOS 製程來實現Level_2 已有的電路,並將其完成為實際電路。 在Level_1 中,鎖相迴路的穩定模擬時間為75 秒,而Level_2 的模擬時間花費了750 秒,為Level_1 的10 倍,但由於使用了行為模式邏輯閘設計了鎖相迴路的功能方塊,因此增加準確度,然後在Level_3 中,我們將其實現為實際電路,但是我們必須花費27720 秒才可以得到系統的穩定,為Level_1 的370倍。 此鎖相迴路的設計特性如下所示: 頻率範圍為2400 MHz 至2500 MHz,輸入參考頻率為10 MHz,每個頻段為20 MHz,所能使用的頻率數目為6,而電流充放電荷磊的電流為1 mA,迴路的頻寬為輸入參考頻率的十分之一,1 MHz,壓控振盪器需要涵蓋鎖相迴路的範圍,因此為2350 MHz 至2550 MHz,而其相位雜訊於1 MHz 偏移頻率(offset frequency)為-110 dBc/Hz。 This thesis implements a 2.4 GHz integer-N frequency synthesizer by using the multi-level methodology. In Level_1, the phase locked loop (PLL) was implemented by behavior model of mathematics to describe the systematic behavior for quickly obtaining the simulation result of PLL system. The logical circuit with behavior model was then performed to design the real circuit in Level_2 which the pure mathematics model in Level_1 was replaced by logical circuit model to make the function closer to the real circuit. Finally, in Level_3, we adopt TSMC CMOS 0.18-µm process to implement the existing circuit of Level_2 to actual circuit. In Level_1, the steady simulation time of the phase lock loop system is 75 seconds, and the simulation time of Level_2 is 750 seconds which is 10 times slower than that of Level_1. However, the accuracy is increased by using the logical circuit instead of mathematic behavior model. Finally, the actual circuit simulation took 27720 seconds in Level_3 design which is 370 times slower than that of Level_1. The specifications of the designed PLL system in the thesis are illustrated as follow: The frequency range is 2400 MHz to 2500 MHz, and input reference frequency is 10 MHz. The number of frequency band is set to 6 with channel bandwidth of 20 MHz. The current of charge pump is chosen as 1mA. The loop bandwidth is the 1/10 of the input reference frequency. The tuning range of voltage controlled oscillator (VCO) needs to cover the range of phase lock loop frequency which covers the frequency range from 2350 MHz to 2550 MHz. The phase noise is -110 dBc/Hz at offset frequency of 1 MHz.
    Appears in Collections:[通訊工程學系碩士在職專班 ] 博碩士論文

    Files in This Item:

    File SizeFormat

    All items in NCUIR are protected by copyright, with all rights reserved.

    社群 sharing

    ::: Copyright National Central University. | 國立中央大學圖書館版權所有 | 收藏本站 | 設為首頁 | 最佳瀏覽畫面: 1024*768 | 建站日期:8-24-2009 :::
    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - 隱私權政策聲明