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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/82343

    Title: 考量老化現象之低功耗設計可靠度分析及優化策略;Aging-Aware Low Power Design Reliability Analysis and Optimization Strategies
    Authors: 陳聿廣
    Contributors: 國立中央大學電機工程學系
    Keywords: 電源閘控;喚醒排程;負偏壓溫度不穩定效應;晶片健康狀況;機器學習;power gating;wake-up scheduling;NBTI;chip health;machine learning
    Date: 2020-01-13
    Issue Date: 2020-01-13 14:46:30 (UTC+8)
    Publisher: 科技部
    Abstract: 隨著IC製程的進步與電晶體體積的縮小,現今的晶片設計往往能達到體積小、功能複雜、效能優越等特性,且被廣泛地運用於可攜帶式裝置如遠端感測器、智慧可攜式裝置等。考量其有限的電源供應,低功耗設計成為實現此類應用不可或缺的技術。另一方面,晶片之老化現象也因製程的縮小及高電源密度/高執行溫度而更為顯著,對晶片的可靠度造成了威脅。為了解決晶片的高功耗及可靠度問題,低功耗(low power)設計及老化考量(aging-aware)設計之相關技術成為晶片設計不可或缺的環節,許多相關的技術也相繼被提出。雖然已提出的技術能降低晶片功耗與增加其可靠度,但在其實作方法(implementation)及動態運作(runtime operation)上,仍有許多高挑戰性的問題尚待解決。因此,在這個三年期的計畫中,我們希望以現有的低功耗及老化考量設計方法為基礎,藉由分析低功耗設計與老化考量設計的關聯性,提出一個適當的整合及電腦輔助設計(computer aided design, CAD)的演算法,使得這些挑戰能有效率的被解決。 我們的計畫目標將解決以下三個困難的問題: (A) 考量負偏壓溫度不穩定效應之電源閘控喚醒排程策略開發 (B) 考量負偏壓溫度不穩定效應且適用於多模組晶片之動態電壓調變策略開發 (C) 利用機器學習演算法對於晶片健康狀況之預估與晶片回收再利用評估演算法開發 此計畫的規劃內容呼應了最新半導體產業的發展趨勢,並利用AI及機器學習等方法改善傳統捷思演算法(heuristic)的不足,以對於大邏輯閘數(large gate counts)的晶片進行高可靠度之低功耗設計。具體而言,我們不僅針對晶片老化現象提出適當的喚醒排程演算法及動態電壓調變演算法,更進一步的提出晶片老化情況之預估方法及晶片回收策略,這些研究成果可應用於消費性電子產品(如:手持式裝置)及大型工業生產機台(如:自動化製造)等,以期能解決現今晶片設計在低功耗設計與老化考量設計中實際遇到的問題。 ;As CMOS technology continuous to scale down, Integrated circuits (ICs) have been wieldy applied to various applications such as remote sensors and smart portable devices due to the benefits of smaller area, higher complexity, and high performance. These applications are usually under limited power budget, which makes low power design as an indispensable technique. On the other hand, high power density and high operating temperature speed-up circuit aging and threaten the integrity of the ICs. To address these problems, low power design techniques and again-aware design methodologies are indispensable in modern IC-design flow. Related techniques are widely investigated and proposed in literature. Although these design techniques can help to reduce power consumption and increase reliability, many crucial challenges in implementation and dynamic operation are still not well resolved. Therefore, in this 3-year proposal, we will deeply study the existing low power design techniques and aging-aware design techniques, find the relevance of them, and propose new integrated methodologies and corresponding computer aided design (CAD) algorithms to efficiently address these crucial challenges. Specifically, the objective of this proposal is to find solutions for the following three crucial problems: (A) NBTI-Aware Wake-Up Strategy for Power-Gated Designs (B) NBTI-Aware Dynamic Voltage Scaling Strategy for Multi-Module Designs (C) Machine-learning Based Circuit Health Estimation Strategy and Algorithms for Recycling Integrated Circuits for Reuse The contents of this proposal work in concert with the demand of the semiconductor industry. Instead of developing traditional heuristic based solutions, we will propose AI / machine learning based methodologies to efficiently handle designs with large gate counts. Specifically, we will develop wake-up scheduling frameworks and dynamic voltage / frequency scheduling frameworks for NBTI-aware designs, and will propose a machine-learning based circuit health estimation method and algorithms for IC recycling for reuse. The proposed methodologies can be adapt to not only consuming electronic products (ex: hand-held devices) but also industrial production machines (ex: automatic manufactory) to solve the challenges in modern IC design industry.
    Relation: 財團法人國家實驗研究院科技政策研究與資訊中心
    Appears in Collections:[電機工程學系] 研究計畫

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