本論文最主要的目的是在如何實現建構出具備簡便操作、高彈性的模擬參數範圍、通道效應逼真、成本降低等特點之通道模擬器，並利用Veilog硬體描述語言，實現在FPGA發展板。通道衰減模擬器為通訊系統在設計與認證上，所不可或缺的一項測試工具，其中Jakes 模型由於具備架構簡單、符合電波散射理論並且能夠呈現都卜勒偏移頻率效應等優點，而廣泛的被應用於Rayleigh 衰減通道的模擬。 在OFDM發射器，提出了一可行的OFDM調變方式的FPGA實現方法，並介紹IFFT與循環字首(Cyclic prefix)加入的具體電路。 This paper principal objective is discuess how can channel simulator include easier operation, more flexible parameter choices, more realistic channel effect, and lower cost, and use the Verilog Hardware Description Language to implement a multipath fading channel emulator on FPGA development board. Fading channel simulator is one of the most important testing equipments for the design and identification of communication systems. Jake’s model is widely used on the simulation of a Rayleigh fading channel. In the OFDM Transmitter, an OFDM modulation structure based on FPGA is Presented.The circuits of IFFT and cyclic prefix joining are also present.
