適用於四階脈波振幅調變資料之高速串列連結關鍵技術設計與實現(I);Design and Implementation of Key Techniques in High-Speed Serial Link for Four-Level Pulse Amplitude Modulation Data

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題名:	適用於四階脈波振幅調變資料之高速串列連結關鍵技術設計與實現(I);Design and Implementation of Key Techniques in High-Speed Serial Link for Four-Level Pulse Amplitude Modulation Data
作者:	鄭國興
貢獻者:	國立中央大學電機工程學系
關鍵詞:	高速串列連結技術;低雜訊時脈產生;高速資料傳輸的訊號完整度;倍數延遲鎖定迴路;鎖相迴路;展頻時脈產生器;連續時間線性等化器;前饋式等化器;決策回饋等化器;資料與時脈回復電路;High-Speed Serial Link Technology;Low-Noise Clock Generation;Signal Integrity of High-Speed Data Transmission;Multiplying Delay-Locked Loop;Phase-Locked Loop;Spread-Spectrum Clock Generator;Continuous Time Linear Equalizer;Feed-Forward Equalizer;Decision-Feedback Equalizer;Clock and Data Recovery Circuit
日期:	2020-01-13
上傳時間:	2020-01-13 14:47:34 (UTC+8)
出版者:	科技部
摘要:	隨著消費性電子產品的快速發展，資料傳輸速率已發展至每秒數十億位元(Gbps)並往更高的速率邁進。作為大量傳輸資料的關鍵技術，高速串列連結技術(High-Speed Serial Link Technology)被廣泛應用在有線收發裝置上，並發展出四階脈波振幅調變(Four-Level Pulse Amplitude Modulation, PAM4)資料。隨著資料速率的快速提升與新資料格式的提出，衍生出的新議題也必須被審視。首先，操作速度加快，意味著更短的時脈週期與更高百分比的時脈扭曲與抖動，同時，四階脈波振幅調變資料的多重準位也會增加資料邊緣占週期的百分比，並嚴重影響收發器動作。因此，高精準的時脈產生器，倍數延遲鎖定迴路(Multiplying Delay-Locked Loop, MDLL)、鎖相迴路(Phase-Locked Loop, PLL)與展頻時脈產生器(Spread-Spectrum Clock Generator, SSCG)將扮演重要的腳色。此外，傳輸速率的增加也意味著更高的通道衰減，同時，四階脈波振幅調變資料的多重準位也壓縮了資料振幅，降低訊號完整度(Signal Integrity, SI)，使得單一的補償機制已不敷使用。因此，連線時間線性等化器(Continuous Time Linear Equalizer, CTLE)、前饋式等化器(Feed-Forward Equalizer, FFE)、決策回饋等化器(Decision-Feedback Equalizer, DFE)和資料與時脈回復電路(Clock and Data Recovery Circuit, CDR)的關鍵技術開發將具有一定的挑戰性與前瞻性。希望藉由確保時脈品質與訊號完整度，開發出適用於四階脈波振幅調變資料的高速串列收發器。在第一年的計畫中，將以90 nm製程設計實現低雜訊時脈產生與高速資料還原技術之關鍵電路。在第二年的計畫中，我們主要的重點在於驗證第一年的相關設計，並將已開發出的技術帶入40 nm製程。於第三年的計畫中，重點在於進行傳送端和接收端的系統整合。 ;With the rapid growing of consumer electronics, data transmission rate has evolved to gigabits per second (Gbps) and move toward higher rate. As a key technology for massive data transmission, high-speed serial link technology is widely applied to wireline transceiver and has developed four-level pulse amplitude modulation (PAM4) data. With the rapid increase of data rate and the introduction of new data format, new issue must also be examined. First, the higher operation speed, meaning shorter clock period and higher percentage of clock skew and jitter. At the same time, the multi-level of PAM4 data also increase the percentage of data edge and affect the transceiver operation seriously. Therefore, a highly accurate clock generator such as multiplying delay-locked loop (MDLL), phase-locked loop (PLL) and spread-spectrum clock generator (SSCG) will play an important role in such applications. In addition, the increase of data rate also means the higher channel loss. At the same time, the multi-level of PAM4 data also decreases the data amplitude and reduces the signal integrity (SI), resulting in a single compensation mechanism is no longer enough for such applications. Thus, the development for key technologies of continuous time linear equalizer (CTLE), feed-forward equalizer (FFE), decision-feedback equalizer (DFE) or a clock and data recovery circuit (CDR) becomes a challenge and prospective work. By ensuring the clock quality and signal integrity, the high-speed transceiver for PAM4 data is developed. In the first year, we would design and implement the key circuit of low-noise clock generation and high-speed data recovery technology with 90 nm CMOS process. In the second year, the main focus is to validate the relevant design of first year and extend the technique to 40 nm CMOS process. Finally, the integrations of transmitter and receiver would be developed in the third year.
關聯:	財團法人國家實驗研究院科技政策研究與資訊中心
顯示於類別:	[電機工程學系] 研究計畫

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