正交分頻多工（OFDM）調變技術普遍被無線通訊規格所採用，其中包含DVB-T，因為OFDM具有較高的頻譜使用效率、較簡單的通道等化及在符元前端插入前置循環字首來抵抗多重路徑干擾(ISI)。然而，OFDM系統對於非同步產生的影響相當敏感，例如符元時序偏移、載波頻率偏移及取樣率偏移。為了解決同步產生的問題，相關方法已被提出來估測及解決OFDM的同步問題，主要為使用前置循環字首訊號相關性之時域估測法及使用Pilots相關性之頻域估測法，不過大部份的演算法假設在靜止環境下，此時發射及接收端為靜止不動的，其通道脈衝響應為非時變，但當發射及接收端處於高速移動環境下時，此時所使用的演算法就不適用，因為通道脈衝響應會隨時間改變。 本論文首先研究探討在高速移動環境下DVB-T系統所面臨的問題，當接收機最大的移動速度高達300 km/hr，此時時變通道會產生都普勒擴展(Doppler Spread)的現象，將破壞子載波間的正交性及訊號間的相關性，一般的靜態環境下的方法已不適用，因此本論文設計一套適用於高速移動環境下DVB-T接收機的同步方法，並使用Modelsim軟體進行驗證且實現於FPGA平台。 OFDM technique is adopted in many standards, including DVB-T, since it exhibits outstanding characteristics in terms of efficiency in spectral utilization, simplicity in equalization and immunity in Inter-Symbol-Interference (ISI). However OFDM system performance is sensitive to synchronization errors including symbol timing offset, carrier frequency offset and sampling clock frequency offset. Typical methods exploiting the correlation of cyclic-prefix in time domain and the correlation of continual pilots in frequency domain have been proposed for estimating and correcting the synchronization errors for OFDM systems. In these methods the channel model is generally assumed to be static, i.e., the transmitter and receiver are in stationary positions and the channel impulse response is time invariant. This assumption is violated especially when the receiver and/or transmitter are in high-mobility environment, i.e., the channel impulse response becomes time varying significantly. In this thesis, we focus on studying on the synchronization problems of DVB-T system when the receiver is in mobility as high as to 300 km/hr. In this scenario, significant time-varying channel impulse response due to large Doppler spread is noticed which causes the loss of subcarrier orthogonality and signal correlation, and the performance of typical synchronization algorithms is evaluated. Finally, a synchronization method, which is more suitable to high-mobility reception, is designed for DVB-T receiver. The implementation of synchronization systems is verified with Modelsim tool and real-time implementation on FPGA hardware.