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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/8314


    Title: 適用於陸規DTTB之可組態QC-LDPC 解碼硬體架構設計;A Configurable Hardware Architecture of Decoder for China’s DTTB QC-LDPC Code
    Authors: 溫品涵;Pin-han Wen
    Contributors: 通訊工程研究所
    Keywords: 線性區塊碼;LDPC;QC-LDPC;陸規DTTB;最小和積演算法;LDPC;QC-LDPC;Sum-Product;Minimum-Sum;China's DTTB;FPGA;Block Code
    Date: 2009-07-07
    Issue Date: 2009-09-22 11:22:58 (UTC+8)
    Publisher: 國立中央大學圖書館
    Abstract: 陸規DTTB以QC-LDPC作通道編碼,本論文利用校驗矩陣以區塊為單位的分佈特性,設計區塊平行處理,並將校驗矩陣的區塊特性儲存於記憶體,以FPGA實現區塊式掃描演算法作為解碼,故調整記憶體中的矩陣特性,即可以此架構使用regular-LDPC的各種碼率或規格的解碼。   本論文提出之可組態的解碼架構,在不降低傳輸效率(Throughput)的情況下,除了節省記憶體的使用程度,同時也降低硬體資源。 More and more broadband broadcasting systems, like 802.11e, 802.11n and China’s DTTB, use multi-rate QC-LDPC codes as their channel coding schemes to support the flexibility in code rate and code length. In this thesis, I present a decoder for multi-rate QC-LDPC codes in China’s DTTB system. The Modified Min-Sum Algorithm, which is adequate to the hardware structure, is used to reduce the complexity of the LDPC decoder while keeping almost the same performance. In the proposed architecture, the decoder can be easily reconfigured for multi-rate or multi-standard as long as the QC-LDPC code is characterized by a base matrix with circular-rotation index. Moreover, the FPGA implementation of this partially paralleled decoder is demonstrated to be more efficient in terms of slices and memory blocks without sacrificing in data throughput.
    Appears in Collections:[通訊工程研究所] 博碩士論文

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