具有優異物理特性的氮化鋁鎵/氮化鎵(AlGaN/GaN)高電子遷移率電晶體(HEMTs)被視為是下世代主要的高功率元件之一。由於金屬-半導體接觸形成之蕭特基(Schottky)閘極結構易導致漏電流過大，使得有效的閘極電壓範圍受到了限制。因此在閘極電極下方沉積一層絕緣層來消除閘極漏電流的設計可使得元件可靠度大為提升，這種堆疊結構被稱為金屬氧化物半導體結構，其能有效地避免蕭特基閘極結構所造成的問題。 本研究藉由非對稱雙極直流脈衝反應性濺鍍系統，沉積氧化鋁薄膜做為金屬氧化物半導體結構的閘極介電材，在不同氧比例與基板溫度條件下，以達到降低介電薄膜/AlGaN界面之缺陷密度，探討氧化鋁薄膜的介電性質的表現。在常溫環境下經由調變氧比例沉積氧化鋁薄膜，雖然不同氬氣與氧氣混合比例氛圍中，其氧化鋁薄膜沉積之介電性質不同，但由於其氧化程度不完全導致介電特性仍較差，後續本研究利用基板升溫進行直流脈衝反應性沉積氧化鋁薄膜於AlGaN/GaN上，經由電容-電壓量測來分析氧化鋁薄膜的性質，並計算其介電常數及界面缺陷密度的變化，目前初步得到在氧比例為0.87 %、基板溫度為300度條件下沉積之氧化鋁薄膜，經由成分組成分析得知其擁有好的化學劑量比，介電常數為3.87，氧化鋁薄膜/AlGaN界面缺陷密度(interface trap density)為2.08×1012 cm-2eV-1，並藉由時間相關介電崩潰測試得知在基板升溫下氧化鋁薄膜介電能力有大幅提升的現象。 ;AlGaN/GaN high-electron-mobility transistors (HEMTs) with excellent physical properties are attractive for high-power devices in next generation. However, metal and semiconductor interface with Schottky contact is easlier to leakage and the effective gate voltage was confined. Therefore, an insulating layer below the gate has to be introduced to eliminate gate leakage and improves devices reliability. This will give rise to the so called Metal Oxide Semiconductor (MOS) structures. In this research, sputtered-Al2O3 thin film as dielectric layer to discuss the interface trap density (Dit) in different deposited oxygen flow (0.54 %, 0.87 %, 1.00 % and 1.55 %) and growth temperature (150 °C and 300 °C) conditions by asymmetric bipolar DC pulse reactive sputtering system. The sputtered films exhibit a stoichiometric composition, which was confirmed using X-ray photoelectron spectroscopy (XPS). Furthermore, using capacitance-voltage (C-V) measurement to analysis and calculate the values of dielectric constant and interface trap density. Ultimately, when the conditions of Al2O3 thin film deposited oxygen flow is 0.87 % and growth temperature at 300 °C, the dielectric constant and interface trap density are 3.87 and 2.08×1012 cm-2eV-1, respectively.
