用於具延遲處理器的8PSK籬柵碼之非同調解碼; Noncoherent Detection for Trellis Coded 8PSK with a Delay Processor

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Title:	用於具延遲處理器的8PSK籬柵碼之非同調解碼;Noncoherent Detection for Trellis Coded 8PSK with a Delay Processor
Authors:	王浩任;Hao-ren Wang
Contributors:	通訊工程研究所
Keywords:	延遲處理器;籬柵碼;trellis code;delay processor
Date:	2009-07-08
Issue Date:	2009-09-22 11:24:15 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	在同調解碼下，具時間延遲處理器之8PSK籬柵碼具有大的最小歐氏距離和優秀的錯誤效能。另一方面，在非同調解碼下，8PSK籬柵碼發展至今，也有著不錯的錯誤效能。本論文對具延遲處理器之8PSK籬柵碼用非同調解碼演算法做檢測。另外，我們在編碼端串接差分編碼器去避免非同調災難碼的產生。為了在非同調解碼的情況下求得最佳的碼，我們也做了碼搜尋。為了讓降低整個調變系統所產生的錯誤蔓延的情形，調整解碼端各層不同的計值的加權值，以得到更好的效能。最後，模擬的結果也顯示出，在高訊雜比的情形下，本篇論文所提出架構的錯誤效能優於8PSK籬柵碼。 Trellis coded 8PSK with a delay processor for coherent decoding has large minimum Euclidean distance and good error performances. On the other hand, trellis-coded 8PSK for noncoherent decoding has been well investigated also. In this thesis, we propose a simple noncoherent decoding algorithm for trellis code with a delay processor. In addition, we use differential encoder to avoid noncoherent catastrophic codes. In order to have the best code, we do code search to find the best code. We use weighting metrics for noncoherent decoding to improve error propagation. Simulation result shows that the error performances of noncoherent decoding for trellis coded 8PSK with delay processor at high SNRs are better than the error performances of trellis-coded 8PSK.
Appears in Collections:	[Graduate Institute of Communication Engineering] Electronic Thesis & Dissertation

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