5G NR- 雙符碼週期模式發射機於FPGA之實現;FPGA Implementation of 5G NR Dual Symbol Period Mode Transmitter

NCUIR > College of Electrical Engineering & Computer Science > Executive Master of Communication Engineering > Electronic Thesis & Dissertation > Item 987654321/89657

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/89657

Title:	5G NR- 雙符碼週期模式發射機於FPGA之實現;FPGA Implementation of 5G NR Dual Symbol Period Mode Transmitter
Authors:	邱顯鈞;Chiu, Hsien-Chun
Contributors:	通訊工程學系在職專班
Keywords:	5G;NR;正交分頻多工;發射機;邏輯電路;FPGA;5G;NR;OFDM;Transmitter;Logic circuit;FPGA
Date:	2022-08-06
Issue Date:	2022-10-04 11:51:14 (UTC+8)
Publisher:	國立中央大學
Abstract:	第五代通訊技術 (5th Generation , New Radio) 於訊號調變之部分，與前代4G通訊皆採CP-OFDM通訊架構。有別於4G 僅使用15kHz子載波間隔(Sub carrier spacing) ，5G 系統在FR1頻段內共有 15,30,60 三種不同頻率間隔由參數集(Numerologies)所決定，可應用於不同場景，且支援通道採混合參數集(Mixed Numerologies)之配置方式。依此特點，本論文著重於3GPP-R16規範之5G下行鏈實體層研究，於N78頻段中設計實驗特定規格之下行鏈，其中同步訊號、廣播通道與控制通道、分享通道採用兩種不同子載波間隔分別為30及15 kHz ，以探討於兩種子載波間隔下的訊框架構之目的，進而藉由硬體描述語言設計邏輯電路來產生對應下行鏈基頻訊號，於FPGA平台實現發射機並進行驗證。實作過程中，針對兩種子載波間隔的符號週期進行IFFT運算，有鑑於此，如何透過時序邏輯、控制訊號及狀態機等解決方案，來達到不中斷的方式產生符合5G 規格訊號OFDM 訊號，為本論文核心探討之問題。 ;In the fifth generation(5G) mobile technology, 3GPP adopted CP-OFDM for waveform modulation which is very similar to the usage in LTE. The difference between these two generations is that LTE only uses a fixed 15 kHz sub-carrier spacing in the physical channel while 5G NR-FR1 supports 15kHz, 30kHz, and 60kHz depending on the factor named Numerologies. Moreover, multi-subcarrier spacing is also supported in the same radio frame structure called mixed (or multi) Numerologies. According to this feature, this paper focuses on studying the 3GPP-R16 specification of the 5G downlink physical layer and designs a downlink transmission channel with a specific configuration in the N78 operating band. The physical channel of SSB/PBCH and PDCCH/PDSCH are set up in different sub-carrier spacing to discuss the frame structure under the resource grid between two sub-carriers (30, 15 kHz). A hardware circuit is designed by Verilog programming language to generate the corresponding downlink baseband signal, and the transmitter is implemented and verified on the FPGA platform. The solution proposed in this paper uses logic circuits to design control signals, state machines, etc., performing IFFT operations on sequences of two symbol period, and generating OFDM signals which meet 5G specifications in an uninterrupted manner is the best result in the experiment.
Appears in Collections:	[Executive Master of Communication Engineering] Electronic Thesis & Dissertation

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