English  |  正體中文  |  简体中文  |  Items with full text/Total items : 75982/75982 (100%)
Visitors : 28187072      Online Users : 137
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version

    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/9227

    Title: 適用於通訊系統之內嵌式數位訊號處理器;An Embedded DSP Core for Communication Applications
    Authors: 李曉屏;Hsiao-Ping Lee
    Contributors: 電機工程研究所
    Keywords: 數位信號處理器;可參數化;低功率;高速的效能;通訊系統應用;Digital signal processing processor;parameterized;low power;high performance;communication systems
    Date: 2001-07-06
    Issue Date: 2009-09-22 11:43:31 (UTC+8)
    Publisher: 國立中央大學圖書館
    Abstract: 在本篇論文中,實現了一顆十六位元的可程式化數位信號處理器。它是專用於通訊系統應用。除了提供一般十六位元數位處理器所具備的基本指令集外,還為了特別的功能硬體設計,提供特殊指令。這使得這顆數位信號處理器更適於計算密集的應用。 我們所提出的數位信號處理器具有幾項優越的特性: 可參數化的架構,高速的效能,和低功率。我們設計了各種模組產生器以產生可變動(configurable)的資料路徑(dat apath)和可重複使用的特殊功能硬體。平行化的架構也加速了效能,在效能測試程式中兩組乘法器串聯加法器減少一半的指令週期。為了減少功率耗損,我們採用許多種低功率設計技巧,如灰碼記憶體定址法和管線分享技巧等。 這顆數位信號處理器的最大工作效能可操作在每秒100百萬指令之 In this thesis, the design and implementation a programmable 16-bit Digital signal processing (DSP) processor are carried out. It is developed specifically for a communication system. Besides providing a basic instruction set, similar to current day 16-bit DSP processors, it contains unique instructions, extra architecture features and special function blocks, which make this DSP processor more efficient for compute-intensive tasks. The proposed DSP processor has some advanced features: a parameterized architecture, high-speed performance, and low power. So various module generators are designed to generate configurable datapath and reusable special function blocks. In addition, we use high degree of parallelism to speed up its performance. The data path contains two Multiply-Accumulate units to reduce half instruction cycles in the performance benchmarks. To reduce power consumption, we use some low power designs such as gray code memory addressing, pipeline sharing techniques. The chip was implemented in a cell-base design method using a 0.35 1P3M cell-library. The maximum performance of NCU_DSP is 100MHz.
    Appears in Collections:[電機工程研究所] 博碩士論文

    Files in This Item:

    File SizeFormat

    All items in NCUIR are protected by copyright, with all rights reserved.

    社群 sharing

    ::: Copyright National Central University. | 國立中央大學圖書館版權所有 | 收藏本站 | 設為首頁 | 最佳瀏覽畫面: 1024*768 | 建站日期:8-24-2009 :::
    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - 隱私權政策聲明