維特比演算法是一種著名的最大相似演算法，這個演算法被大量使用在通道編碼、等化器與消息編碼中，因此我們希望能設計很優秀的維特比解碼器。但是，近日來「上市時間」與「完整驗證」這兩個概念日趨重要，然而使用傳統設計方法是無法同時滿足這兩個概念的需求，因為針對不同的規格同樣的模組，我們需要去重新設計與驗証。然而藉由「可規劃式設計」這個新方法，我們只需要設計一塊硬體，對於不同的規格，我們只需要重新規劃控制電路即可。 在本論文中，我們著重於可規劃式維特比解碼器的發展。我們先介紹我們所提出的可規劃式維特比解碼器。在設計的過程中，我們會探討實現上的要素且選定我們所要採用的架構；接著我們以Matlab程式驗證整個解碼運作的過程，並以Verilog硬體描述語言來模擬及驗證電路的正確性。最後，我們以Altera FLEX 10K200E來實現我們的設計。 Viterbi algorithm is a famous Maximum-likelihood algorithm. This algorithm is widely used in Channel Coding, Equalizers and Source Coding. Therefore, we wish to design a high performance Viterbi decoder. But, the concepts of “Time-to-Market” and “Well-Verification” become more and more important in these days. However, there is a trade-off between these two concepts. In traditional design methodology, we must re-design the same modules for different specifications, but a new design methodology, called “Reconfigurable Design”, is introduced. By this method, we only design a fixed hardware only for different specifications. Hence, we just reconfigure the part of the control circuits in the hardware. In this thesis, we focus on the development of the Reconfigurable Viterbi Decoder (RVD). Hence, we will introduce the concept of RVD. In the realization of RVD, we discuss the implementation issues and the proposed architecture firstly. Then, the decoding process is simulated by using Matlab and verified by Verilog HDL. Finally, the decoder is realized by the FPGA device.
