近年來，隨著網路的蓬勃發展，網路上的應用也愈趨多元化，除了傳統的資料數據之外，像是多媒體資訊、VoIP、視訊會議、遠距教學、VPN等此類的新一代以資源需求為主的多媒體應用程式，更是以驚人之速度快速成長，網路使用者若能依據不同應用的應用特性來分配頻寬的多少與使用頻寬的優先權，將可對網路資源作合理而有效的運用。 StrongARM-based網路處理器已漸漸成為傳統以ASIC為主要來處理用戶層面封包(user plane)的另一可程式化的選擇。它利用協同處理器(coprocessors)協助處理原本一般用途處理器(general-purpose processor)所負責的用戶層面的封包。在本論文中我們提出基於Diffserv Edge Routers分類及排程處理效能之研究，實作於StrongARM-based Core嵌入式開發平台。本論文分別採用Intel兩種不同系列的網路處理器做為我們的研究平台，研究差別式服務封包在NPE-based Ethernet及Microengine處理上的流程及造成效能瓶頸的所在。在封包處理上，採用聚集(Aggregate)和PHB(Per Hop Behavior)進行分類及排程，以提供一定程度上的QoS保證。另外，我們也指出在頻寬管理方面採用不同的佇列排程方式所產生的效能瓶頸。其中HTB的產出標準差遠比CBQ的產出標準差小13.98倍。以及經由內部測試，量測出在Diffserv封包傳輸，當涉及眾多規則表查詢及計算時，SRAM和Microengine則分別為IXP2400效能瓶頸，最後針對IXP425平台設計9項實驗驗證本系統的正確性並探討其效能。 In recent years, with the flourishing development of the network, the network applications tend to pluralism too. Besides traditional materials data, as if the application program of multimedia, VoIP, Video Conference, long-distance teaching, VPN, etc., these new multimedia application program on the basis of resource request grow up fast at the surprising speed even more. If network user can distribute the bandwidth and the usage priority according to different application characteristics that use, can make rational and effective application to resources of the network. Network Processors are emerging as a programmable alternative to the traditional ASIC-based solutions in scaling up the user-plane processing of network services. They serve as co-processors to offload user-plane traffic from the original general-purpose microprocessor. In this work, we illustrate the classification and scheduling performance research on Diffserv Edge Routers. And implement on StrongARM-based core embedded development platforms. We adopt Intel two different series Network Processors as our research platforms. Research the processing procedures and performance bottlenecks of Differentiated Service packets on NPE-based Ethernet and Microengines respectively. In the packets processing procedures, adopt aggregate and PHB to offer the guaranteed QoS. Besides, we also point out the performance bottlenecks by adopting different Queuing scheduling on bandwidth management. And through internal benchmarks, we found that when the Diffserv packets involve several rules and calculations, SRAM and microengine are the main components of the performance bottlenecks. Finally, we design 9 experiments to verify the correctness and performance issues of our system.
