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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/9269


    Title: 適用於晶片間通訊之高速傳輸介面;High Speed Serial Link for Inter-Chip Communication
    Authors: 喻柏莘;Bo-Shen Yu
    Contributors: 電機工程研究所
    Keywords: 鎖相迴路;低電壓差動訊號;高速傳輸介面;LVDS;phase locked loop;high speed serial link
    Date: 2002-07-05
    Issue Date: 2009-09-22 11:44:20 (UTC+8)
    Publisher: 國立中央大學圖書館
    Abstract: 由於製程技術的進步,CMOS積體電路的操作頻率及電路複雜度也隨著增加。使得晶片內部的邏輯閘及連結外部的輸入/輸出介面間的頻寬差距到達嚴重的比例。因此,連接晶片間的傳輸通道時常限制了系統的效能,這些系統包括網路的切換器、路由器、處理器和記憶體間的介面及多處理器的傳輸通道。 在此論文中,我們有兩個研究主題。首先,我們將簡單的說明及討論通道建模、介面電路的雜訊來源、二元及調變訊號的比較及低電壓差動訊號標準。依據這些知識,我們提出一個符合低電壓差動訊號標準的2.5 Gbps收發器。接著,我們也將提出一個新的脈波邊緣位置調變技術及使用此技術的收發器,相較於一般常用的脈波振幅調變技術,脈波邊緣位置調變技術使用在一個傳輸符碼內的脈波邊緣位置來代表數位資訊。使用此技術的收發器將可工作在5 Gbps的位元傳輸率,實現此收發器的電路技術及設計概念也將再論文中說明。 論文中,我們將實現一個符合低電壓差動訊號標準2.5 Gbps的傳送器。此傳送器是使用0.25μm的製程製作且在2.5V的供應電壓下可以操作在2.5 Gbps,另外晶片面積則為1.348*0.986mm2。使此設計能工作在2.5 Gbps的計技術包括使用點對點的傳輸、在傳送器將數位資料串列傳輸而在接受器則將串列資料使用時脈資料恢復電路轉換回並列的數位資料。 Due to process technologies scale-down, the operating frequency and circuit complexity of CMOS VLSI increase. The growing gap between on-chip gates and off-chip I/O bandwidth is reaching the critical proportions. Therefore, the interconnects between chips often limit the performance of a system in application such as network switches, routers, processor-memory interfaces, and multi-processor interconnection. For this reason, to integrate high speed serial links on chips can reduce the pin/wire count, and power budget of a system significantly. There are two major topics in this thesis. First, we will focus on the study of channel modeling, signalling noise sources, binary versus modulation signalling, and low voltage differential signalling (LVDS) standard. Base on these considerations, we will propose the 2.5 Gbps transceiver that conforms to the LVDS specifications. Second, we will propose a transceiver architecture that uses proposed edge-position modulation (EPM), In contrast with pulse-amplitude modulation (PAM), EPM uses the pulse edge transition site in the transmitted symbol to denote digital codes. This transceiver for the physical layer of a serial link will have a data bandwidth of 5 Gbps. The circuit design and operational concept for the transmitter and receiver will be described. In this thesis, a 2.5 Gbps transmitter has been implemented. It is compatible with the low voltage differential signalling (LVDS) standard. In a TSMC 0.25-μm CMOS technology, the transmitter circuit operates at 2.5 Gbps on a 2.5V power supply and occupies an area of 1.348*0.986mm2 . The technique to achieve 2.5 Gbps data rate is using point-to-point topology with serialization of data bits in transmitter and deserialization with tracking phase clock/data recovery techniques in receiver.
    Appears in Collections:[電機工程研究所] 博碩士論文

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