3D快閃記憶體晶片測試平台開發;Development of a Testing Platform for 3D Flash Memory Chips

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題名:	3D快閃記憶體晶片測試平台開發;Development of a Testing Platform for 3D Flash Memory Chips
作者:	李浩源;Lee, Hao-Yuan
貢獻者:	資訊工程學系
關鍵詞:	快閃記憶體;嵌入式硬體;Flash memory;Embedded hardware
日期:	2023-07-25
上傳時間:	2024-09-19 16:49:41 (UTC+8)
出版者:	國立中央大學
摘要:	3D快閃記憶體晶片在容量和讀寫速度方面不斷提升，產品生命週期不斷縮短，這促使晶片製造商需要投入更多人力來縮短韌體開發及測試驗證時間。為此我們開發了一個用於3D快閃記憶體的測試平台，目的在於能夠根據待測晶片規格，自動產生並輸出韌體程式碼的功能指令以及測試流程的程式腳本，讓使用者得以快速進行功能指令的設定和記憶體特性分析，同時也確保了程式的開發效率和提升可靠性。此一平台可驗證TLC模式下基礎功能指令(如擦除、寫入、讀取、讀取重試)的正確性，同時可進行TLC、SLC以及TLC與SLC混用模式下的特性測試，並透過實驗來驗證不同模式下的耐久性。藉此平台，我們進行一系列的3D快閃記憶體的測試，在TLC模式下，當對WL0和WL1進行3,000次P/E操作後，讀取WL0直到發生致命錯誤時，相較於沒有Close WL的WL0，具有Close WL的WL1的讀取次數增加了1.23倍。此外，當P/E超過3000次後，無論是否有Close WL，在讀取WL0與WL1直到發生致命錯誤時，WL0的讀取次數整體上都高於WL1。這證明了P/E次數對於記憶體的讀取次數具有重要影響。以此驗證了我們所開發的3D快閃記憶體的測試平台的實用性。;3D NAND flash memory chips have been continuously advancing in terms of capacity and read/write speed, leading to shorter product life cycles. This necessitates chip manufacturers to allocate more resources to reduce firmware development and testing/validation time. To address this, we have developed a testing platform specifically designed for 3D NAND flash memory. The platform aims to automatically generate and output firmware code for functional instructions and program scripts for test procedures based on the specifications of the target chip. This enables users to quickly configure functional instructions and analyze memory characteristics, while ensuring efficient program development and improved reliability. The platform verifies the correctness of basic functional instructions (such as erase, program, read, and read retry) in TLC mode and conducts feature testing in TLC, SLC, and mixed TLC/SLC modes. Additionally, it utilizes experiments to validate durability in different modes. Using this platform, we conducted a series of tests on 3D NAND flash memory. In TLC mode, after performing 3,000 P/E cycles on WL0 and WL1, the read count of WL1 with Close WL was found to be 1.23 times higher compared to WL0 without Close WL, until a fatal error occurred during read. Furthermore, beyond 3,000 P/E cycles, regardless of Close WL, the overall read count of WL0 was higher than WL1 when reading until a fatal error occurred. This demonstrates the significant impact of P/E cycles on the read count of the memory. These findings validate the practicality of the developed testing platform for 3D NAND flash memory.
顯示於類別:	[資訊工程研究所] 博碩士論文

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