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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/9410

    Title: 先進加密標準演算法之IP模組元件設計與驗證;IP reuse design and Verification for Advance Encryption Standard algorithm
    Authors: 柯宏親;Hung-Chin Ke
    Contributors: 電機工程研究所
    Keywords: 影像加密;矽智財產權;場控邏輯閘陣列;先進加密標準;FPGA;Reuse;IP;Image encryption;AES
    Date: 2002-06-04
    Issue Date: 2009-09-22 11:47:10 (UTC+8)
    Publisher: 國立中央大學圖書館
    Abstract: 為了要加速系統晶片之設計,智產設計之再利用(IP reuse)成為必需之工具及技術,本論文針對Advance Encryption Standard (AES) 演算法的特性,利用IP reuse 的概念去設計出一個高效率的128位元的區塊加密器(AECs),這個加密器之throughput 可以逹到1163Mb/s,我們採用加解密核心分開設計,以增加系統的彈性並利用平行處理的架構和回授電路的設計,有效可以加快加解密速度和降低硬體的複雜度並設計一個 4 clocks 存取的移位暫存器去減少I/O pins 接腳數,以致不會造成成本之浪費. 我們利用VHDL,Synplify,ModelSim,MaxplusII,and Quartus II來設計,合成及模擬AECs,最後使用Field Programmable Gate Array(FPGA)來實現,其加密核心之Logic element(LE)總數為1437,其工作頻率為100MHz,資料處理量約為1163Mbps,解密核心之LE總數為1895個,其工作頻率為90MHz,資料處理量為900Mb/s,根據此特性應用在影像來逹成加解密的效果. In order to speed up the pace of system on a chip (SOC) development, designers intend to integrate intellectual properties (IP) into the chip. IP in chip design industry refers to pre-designed and pre-verified building blocks that can be reused for faster time-to-market. In this thesis, the research is focus on the characteristic of Advance Encryption Standard (AES). Using the IP reuse concept of AES to implement the 128bits block cipher efficiently and increase flexibility of Encryptor / Decryptor, we design Encryption Core and Decryption Core separately. Moreover, because the AES algorithm is the iterative encryption algorithm, we just only design one encryption/decryption architecture, pipeline architecture and using the feedback circuit to reduce the hardware complexity. In order to reduce the I/O pins, we design the shift register with four clocks cycles imports the Plaintext 128 bits and Secret Key 128 bits. To realize the AECs, we use VHDL, Synplify, ModelSim, and MaxplusII for designing, synthesizing and simulation. Field Programmable Gate Arrays (FPGAs) are chosen as our target hardware environment. The encryption core design of AECs for area requires 1437 logic cells. The maximum operating clock is 100Mhz and the corresponding data throughput is about 1163Mbit/s. the decryption core design of AECs for area requires 1895 logic cells. The maximum operating clock is 90Mhz and the corresponding data throughput is about 900Mbit/s. According to the characteristic, we can apply to the field of Image encryption.
    Appears in Collections:[電機工程研究所] 博碩士論文

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