三維半導體元件模擬器之開發及SOI MOSFET特性分析;Development of 3-D semiconductor device simulator and analysis of SOI MOSFET

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > Electronic Thesis & Dissertation > Item 987654321/9536

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/9536

Title:	三維半導體元件模擬器之開發及SOI MOSFET特性分析;Development of 3-D semiconductor device simulator and analysis of SOI MOSFET
Authors:	黃朝新;Chau-Hsin Huang
Contributors:	電機工程研究所
Keywords:	三維半導體;元件模擬;SOI MOSFET;3D decoupled method;connection-table;three-dimensional device simulator
Date:	2003-06-19
Issue Date:	2009-09-22 11:49:54 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	本論文主要以階層化不完全LU法(L-ILU method)的稀疏矩陣解法器配合分離法(decoupled method)而建立一套三度空間的半導體元件模擬器。為了印證所開發元件模擬器的正確性，我們將使用Medici和Davinci軟體來印證。而在元件應用上，我們使用三度空間的元件模擬器來模擬真實的SOI元件，並使用body-tied的等效方式來使SOI元件能更穩定的操作。並且，我們也利用SOI DTMOS和在SOI元件上使用不同的閘極結構來使SOI元件能達到低功率和高效率的特性。其間，為了節省記憶體空間，我們也開發了一套能近似三度空間特性的二維等效模擬軟體。 In this thesis, we use the Levelized Incomplete LU method and decoupled method to build up a three-dimensional device simulator. Moreover, we use the Medici and Davinci software to prove the validity of our 3-D device simulator. In 3-D device application, we use the three-dimensional device simulator to simulate the real silicon-on-insulator (SOI) device. Moreover, we use the body-tied method to obtain more stable device operation. Furthermore, we use the methods of SOI DTMOS and different gate structures to obtain the characteristics of lower power and high efficiency. In the meantime, we developed a quasi-3D device simulator to represent 3-D characteristics by using a 2-D device simulator for memory reduction.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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