H.264 影像解碼之系統設計及硬體軟體整合平台; A System Level Design of H.264 video decoder with Hardware and Software Integration Platform

NCUIR > College of Electrical Engineering & Computer Science > Executive Master of Electrical Engineering > Electronic Thesis & Dissertation > Item 987654321/9964

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/9964

Title:	H.264 影像解碼之系統設計及硬體軟體整合平台;A System Level Design of H.264 video decoder with Hardware and Software Integration Platform
Authors:	林宏龍;Hung-long Lin
Contributors:	電機工程研究所碩士在職專班
Keywords:	解碼;嵌入式系統;H.264;decoder;embeed system
Date:	2008-12-31
Issue Date:	2009-09-22 12:01:59 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	本碩士論文中，利用SOCLE CDK2007 平台實現了一個H.264/AVC 解碼器，經由複雜度分析發現，除區塊濾波器為其中較佔據系統資源其中之一的模組，所以我們選擇使用硬體實現以及搭配軟體處理其他部分，第6 章表格中有列出幾個架構效率比較，經過幾篇論文中的效率比較，我們選擇了一個效率較佳的除區塊濾波電路來做硬體實現，此架構中因為垂直濾波跟水平濾波做平行處理，此除區塊濾波電路利用幾組暫存器的搬移實現了平行處理垂直以及水平濾波，另外本文在實現過程中也發現除區塊電路的平行處理上控制電路做了修改之後可以比原先參考架構縮短了30%的時間去完成一張圖片的解碼。第6 章會提到硬體修正前以及修正後的結果，並且將解碼的時間與多篇paper 做一個比較。關於色差轉換部分由於其計算方式使用到浮點運算在最佳化初期占了整體效能的30% 所以也選擇以硬體實現。軟體部分使用網路上的原始程式，搭配ARM 的profile 分析，針對其中各個模組個別去做最佳化以及降低記憶體存取的頻率，使用內部暫存器去做各個區塊的運算。在兩個硬體模組以硬體實現以後整合到系統整合版上之後必須考慮最佳化程序: 1. 系統周邊最佳化，本文中第6 章有提到我們針對實現H.264 播放影像針對的LCD 以及外部記憶體SDRAM，加上系統PLL 控制以達成最佳化的目的。 2. 硬體效能量測，本文第6 章節提到硬體執行所需要的時間，根據RTL 模擬可以得到改善後的結果。 3. 未來必須針對軟體且利用ARM 公司所提供的profile 軟體去預估軟體執行過程的最遲緩的地方做演算法最佳化。經過以上處理程序系統上撥放效能可以從QCIF 0.5fps，提升到10fps。 In this master thesis, this uses the platform of SOCLE CDK2007 to implement an H.264/AVC decoder. Through the complexity of analysis of previous study, the De-block Filter module should be one of the modules which occupy more system resource, so that we decide to use hardware to implement this module. Chapter6 sets out a few forms to in the framework of De-block efficiecy, after several in the efficiency of comparison, we have chosen a better efficiency in a addition to De-block Filter circuits to do implementation. The Filter circuit in addition to block the use of several 4x4 registers of the move between register to achieve the parallel processing of the vertical and horzinortal Filtering. Also in the realization of the implementation of this article, we found the parallel processing control circuit can be done to amend the original frame De-block Filter time, which can reduce 30% the processing time of De-block Filter than original architecture. Chpater 6 will be referred to the amendment and make a Filtering time comparison to more paper. For YUVtoRGB which occupy 30% system performance, so we decide to implement it by Hardware. In the software part of the use of ARM’s profile analysis, we found the conversion of YUV to RGB also wasted 30% CPU time, so we will use hardware to implement the YUV to RGB module. After implementation of two hardware module, we must to consider optimize process before hardware and software integrate into the system board: 1. The best system around, and in this article are referred to Chapter 6 players for the realization of H.264 Video, we focus on LCD, external SDRAM and system PLL optimization. III 2. Hardware performance measurement, Chapter 6 of this article to the hardware section execution time, according to the RTL simulation we can get the improved result. 3. In the future, we should use ARM’s profile software to estimate the software execution process and find out the CPU execution cycles to improve the wasted CPU cycles by software algorithm. After performance enhancement which can improve QCIF 0.5fps to 10fps in H.264 system.
Appears in Collections:	[Executive Master of Electrical Engineering] Electronic Thesis & Dissertation

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