本論文主要研究內容為寬頻放大器及V頻帶接收機之前端電路研究，設計的晶片皆利用WIN 0.15 um pHEMT與TSMC 0.18 um CMOS製程研製。論文電路包含3-55 GHz分佈式寬頻放大器、15-50 GHz分佈式寬頻放大器、35-65 GHz串接式寬頻放大器、V頻帶三級串接式低雜訊放大器、27.1 GHz變壓器回授型壓控振盪器、V頻帶次諧波二極體混頻器以及V頻帶次諧波電阻性混頻器。 寬頻放大器設計包含三個電路，其中3-55 GHz分佈式寬頻放大器利用疊接式放大器及電容分容的技巧來設計，量測頻寬為1-53 GHz，功率增益為9.43 dB且增益平坦度為正負2 dB，輸入輸出返回損耗皆大於2 dB；15-50 GHz分佈式寬頻放大器利用有限接地共平面波導的優點及二級串接分佈式架構來設計，量測頻寬為13-54 GHz，功率增益為10.45 dB且增益平坦度為正負1.2 dB，輸入輸出返回損耗皆大於5 dB；35-65 GHz串接式寬頻放大器利用四級串接放大器及自给偏壓的方式來設計，量測頻寬為28-59 GHz，功率增益介於13至26 dB，輸入輸出返回損耗皆大於3.9 dB。 V頻帶接收機前端電路包含四個電路，其中V頻帶三級串接式低雜訊放大器利用源極電感退化技巧來達到輸入及雜訊匹配的最佳化，頻率在60 GHz，功率增益為24.35 dB，輸入輸出返回損耗皆大於2.58 dB，雜訊指數為3.2 dB；27.1 GHz變壓器回授型壓控振盪器利用變壓器來獲得較低的相位雜訊，在1 MHz的相位雜訊為-94 dBc/Hz，輸出功率為-15 dBm，可調頻率範圍為847 MHz；V頻帶次諧波二極體混頻器，在射頻訊號60 GHz時有最小轉換損耗12.075 dB，輸入功率1-dB壓縮點為 4 dBm，輸入三階截斷點為15 dBm；V頻帶次諧波電阻性混頻器，在射頻訊號60 GHz時有最小轉換損耗10.593 dB，輸入功率1-dB壓縮點為9 dBm，輸入三階截斷點為13 dBm。 The work in this thesis focuses on broadband amplifiers and V-band RF receiver front-end circuits. The designed circuits include three broadband amplifiers with different topologies and bandwidths, a V-band low noise amplifier, a 27.1 GHz transformer feedback voltage control oscillator, a V-band subharmonic diode mixer and a V-band subharmonic resistive mixer. Those designs were fabricated in WIN 0.15 um pHEMT technology and TSMC 0.18 um CMOS process. The thesis first addresses the performance and design of three different broadband amplifiers. The 3-55 GHz distributed amplifier made use of a pHEMT cascode gain cell capacitively coupled to the gate line. The circuit has been experimentally verified for its functionality. This circuit achieved a gain of 9.43±2 dB from 1 to 53 GHz, and the input/output return losses of more than 2 dB. The 15-50 GHz distributed amplifier was implemented with two-cascaded three-stage topology and the finite-ground coplanar waveguide for the transmission line design. The measured result showed this circuit had a gain of 10.5±1.2 dB from 13 to 54 GHz, and the input/output return losses of more than 6 dB. The 35-65 GHz broadband amplifier was designed with the four-cascaded single-stage scheme to achieve the high gain in the high frequency. The self-bias architecture was also used for the single positive supply operation. The cascade amplifier exhibited a gain of 13-26 dB in the bandwidth from 28 to 59 GHz, and the input/output return losses of more than 3.92 dB. The thesis further addresses V-band RF receiver front-end circuits. The V-band three-stage-cascaded LNA architecture was a derivative of the inductive source degenerated topology. The LNA achieved a gain of 24.35 dB at 60 GHz, a noise figure of 3.2 dB, and the input/output return losses of more than 2.58 dB. The 27.1 GHz transformer feedback voltage controlled oscillator utilized the transformer to lower the phase noise. This voltage controlled oscillator obtained a tuning range of 847 MHz, an output power of -15 dBm, and the phase noise of -94 dBc/Hz at 1 MHz offset. The V-band subharmonic diode mixer was based on an antiparallel Schottky diode pair. The design exhibited a 12.075 dB conversion loss at the RF frequency of 60 GHz, the LO frequency of 27.1 GHz, and the IF frequency of 5.8 GHz. The measured input power at the 1-dB gain compression point was 4 dBm, and the input third order inter-modulation intercept point was 15 dBm. The V-band subharmonic resistive mixer achieved a 10.593 dB conversion loss at the RF frequency of 60 GHz, the LO frequency of 27.1 GHz, and the IF frequency of 5.8 GHz. The measured input power at the 1-dB gain compression point was 9 dBm, and the input third order inter-modulation intercept point was 13 dBm.
