在傳統設計流程中，電源電壓降(IR-drop)效應往往需要等到電晶體(Transistor)層級才用SPICE或電源網絡分析工具分析出來。因此，在邏輯閘層級或者電晶體層級實現高階電源電壓降分析，可以協助用者早期修正相關問題。本實驗室先前已經發展一個邏輯閘層級的EDA工具，在只使用現有的標準元件庫(standard cell library)下，就可以估測到理想的電流波形。在本篇論文中，我們依照實驗室先前提出的方法，在不需要做額外的元件特性描述萃取的情況下，提出了估測動態電源電壓降的方法。由於只要在邏輯閘層級就可以獲得我們所需要的輸入資料，因此可以很容易的結合在現今的設計流程之中。在我們的實驗結果之中，電源電壓降的估測誤差可控制在10%附近，是個又快速又精準的方法。 In the traditional design flow, the IR-drop effects are often analyzed at transistor level by SPICE simulation or rail-analysis tool. If designers hope to fix IR-drop problems at early design stage, high-level supply current model is the key to analyze the IR-drop value. A supply current waveform estimation method using existed standard cell library is proposed in the previous work of our laboratory. Based on that work, this thesis proposes a dynamic IR-drop estimation method without additional characterization efforts for each standard cell. This approach can be easily embedded into current EDA design flow because all the required input data are available at gate-level. As shown in the experimental results, the estimation errors of IR-drop values are around 10%. They have demonstrated that this is indeed a fast and accurate approach for high–level IR-drop estimation.
