| 摘要(英) |
With the shrinking of device size in deep submicron process, impacts of process variation for circuit performance are more and more important, especially for analog circuits. Therefore design for manufacturability (DFM) and design for yield (DFY) become popular research topics. The consideration of process variation effects is the main issue of DFM and DFY. If we can use the device parameter variation analysis to evaluate the circuit performance due to the process variations in the beginning of designing a circuit system, we will get better tolerance to increase yield rate and reduce production cost.
In order to analyze the impacts of process variations, one of the common approaches is using Monte Carlo (MC) analysis. According to the statistical model of transistor parameters, lots of samples are selected with different parameter values to perform transistor-level simulations and observe the shift of output performance. If the number of samples is large enough, this approach can accurately estimate the impacts of process variations. However, since transistor-level simulation often required long simulation time, repeating hundred times of simulations are too expensive for time to market.
In this thesis, we propose an efficient way to build an accurate analog behavioral model for phase locked loop (PLL) circuit, which is more sensitive in performance due to process variations. This behavioral model can reflect the performance shift under process variations with this behavioral model, we can use the device variation model from foundry to conduct a high-level Monte Carlo analysis and reduce the simulation time significantly. Besides the speed improvement over HSPICE simulation, our approach also has good accuracy. Therefore, this approach can help designers to estimate the effects of process variations more efficiently. |
| 參考文獻 |
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