 |
|
|
|
以作者查詢圖書館館藏 、以作者查詢臺灣博碩士 、以作者查詢全國書目 、勘誤回報 、線上人數：89 、訪客IP：18.191.111.130
姓名 陳冠宏(Kuan-hung Chen) 查詢紙本館藏 畢業系所 電機工程學系 論文名稱 應用於高效率單電子元件鍺量子點之研製:鍺量子點定位與定量之探討
(Positioning and numbering Ge quantum dots for effective single-electrondevices)相關論文 檔案 [Endnote RIS 格式]
[相關文章]
[文章引用]
[完整記錄]
[館藏目錄]
[檢視]
- 本電子論文使用權限為同意立即開放。
- 已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
- 請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。
摘要(中) 本論文研究討論利用選擇性氧化複晶矽鍺形成鍺量子點的技術。以及調變奈米溝渠
的幾何結構，有效地控制鍺量子點顆數與位置。鍺量子點形成的位置與複晶矽鍺的氧化截止點有強烈的相關性，利用不同的奈米溝渠側壁(二氧化矽材料或氮化矽)材料與溝渠的大小，可以有效地控制鍺量子點形成的位置。當奈米溝渠側壁為二氧化矽且寬度在30nm 以下時，可觀察到單一顆球形的單晶鍺量子點分布在奈米溝渠的中間，量子點大小為12.5±2.8 nm。在寬度同樣為小於30 nm，而奈米溝渠側壁為氮化矽的條件下，鍺量子點的分布則是隨機的，有的分布在奈米溝渠的中間，有的則在奈米溝渠的邊緣，量子點大小為9.7±1.5 nm。當奈米溝渠寬度為50 nm 或70 nm 時，不論是側壁為氮化矽還是二氧化矽，這兩個條件的鍺量子點皆分布在奈米溝渠的兩側邊緣，其鍺量子點大小分別為11.4±0.9 nm 與8.3±1.4 nm。利用此方法，我們可以氧化奈米溝渠中的複晶矽鍺，形成單一顆鍺量子點供單電子電晶體應用；或兩顆鄰近的量子點做為偶合量子點之用。
摘要(英) This thesis demonstrates that controlling the position and the number of Ge quantum dots (QDs) embedded in SiO2 or Si3N4 tunnel barriers in a self-organized manner is realized by oxidizing SiGe nano-trenches. A single Ge QD in the core or double QDs at the edges of oxidized SiGe trenches could be effectively modulated by the trench geometry and the materials adopted for spacer and bottom layers. For SiGe trenches with SiO2 spacers having an trench width of less than 30 nm, Ge QDs line up in the center of oxidized trenches with an average dot size of 12.5 ± 2.8 nm. In contrast, for SiGe trenches with Si3N4 spacers having the same trench width, smaller Ge QDs (9.7 ±?1.5 nm) reside randomly either in the center or near the edges of oxidized trenches. For SiGe trenches with width of 50 or 70 nm, we observed remarkable twin Ge QDs precipitation closely along each boundary between the trench and the nearby SiO2 and Si3N4 spacers, respectively, with an average dot size of 11.4 ± ?0.9 nm and 8.3 ±?1.4 nm. Using this method, it is reasonable to expect that effective single-electron transistors and coupled QD devices could be realized.
關鍵字(中) ★ 奈米溝渠
★ 矽鍺
★ 量子點關鍵字(英) ★ quantum dots
★ nanotrench
★ selective oxdiation論文目次 目錄
中文摘要 .................................................i
英文摘要 ................................................ii
致謝 ...............................................iii
目錄 ................................................iv
圖目錄 ................................................vi
第一章 簡介與研究動機 ...............................1
1-1 半導體元件發展歷史 ...............................1
1-2 單電子元件的誕生 ...............................2
1-3 量子點的材料 ........................................3
1-4 矽材料的量子點 ........................................5
1-5 研究動機 ........................................7
第二章 關鍵製程與製作流程 ..............................18
2-1 前言 ................................................18
2-2 溝渠形狀 .......................................18
2-3 製作流程 .......................................19
第三章 鍺量子點的分布情形 ..............................24
3-1 穿透式電子顯微鏡 ..............................24
3-2 實驗結果 .......................................24
3-3 TSUPREM模擬 .......................................25
第四章 共振穿隧二極體元件製作與電性量測 ............41
4-1 元件製作流程 .......................................41
4-2 電性量測 .......................................41
4-3 製程討論 .......................................43
第五章 總結與未來展望 ..............................49
參考文獻 ................................................51
著作目錄 ................................................54
圖目錄
圖1-1. 各式先進元件發展及運用趨勢 (ITRS,2003) ...........10
圖1-2. 單電子電晶體之等效電路示意圖 ....................10
圖1-3. SET示意圖、能帶圖、I-V 特性曲線圖 ...........11
圖1-4. 日本NTT將單電子電晶體與金氧半場效電晶體整合.......11
圖1-5(a). 東京大學團隊提出的量子點接觸式單電子電晶體製作流程示意圖 ................................................12
圖1-5(b). 經過(a)TMAH 與(b)SC1濕蝕刻後SEM影像與剖面結構示意圖。 ................................................12
圖1-6(a). 普林斯頓大學團隊所製作的算盤串珠狀單電子電晶體結構示意圖。 .......................................13
圖1-6(b). (a)氧化前 (b)氧化後奈米細線的SEM影像。 ..13
圖1-7. 量子點與穿隧接面的示意圖 ....................14
圖1-8. 利用 E-Beam 不穩定性搭配濕蝕刻製作出 SET 之示意圖 ................................................14
圖1-9. 結構剖面圖 .......................................15
圖1-10. TEM剖面圖與EDX量測結果 .....................15
圖1-11. 完全氧化完TEM剖面圖與俯視圖 .....................16
圖1-12(a). 奈米線的長寬分別為1 MM與70 nm(a) SEM俯視圖(b)TEM俯視圖 ................................................16
圖1-12(b). 奈米線的長寬分別為150 nm與40 nm 的TEM俯視圖 ..17
圖2-1. 蝕刻後溝渠剖面的SEM圖 .....................21
圖2-2. 複晶矽鍺沉積後的SEM圖 .....................21
圖2-3. 複晶矽鍺沉積示意圖 ..............................22
圖2-4. 回蝕後的SEM圖 ..............................22
圖2-5. 將C4F8 流量由90 sccm 增加至120 sccm，蝕刻複晶矽後，溝渠剖面SEM影像 .......................................23
圖3-1. 溝渠側壁與底部皆為二氧化矽條件的TEM Plane-view ..29
圖3-2(a). 3-1圖中A的放大圖 ..............................30
圖3-2(b). 3-1圖中B的放大圖 ..............................30
圖3-3. 不平坦的矽鍺膜氧化示意圖 .....................31
圖3-4. 溝渠側壁為二氧化矽，底部為氮化矽條件的TEM Plane-view ................................................32
圖3-5(a). 3-4圖中A的放大圖 ..............................33
圖3-5(b). 3-4圖中B的放大圖 ..............................33
圖3-6. 側壁與底部為氮化矽條件的TEM Plane-view ............34
圖3-7(a). 3-6圖中A的放大圖 ..............................35
圖3-7(b). 3-6圖中B的放大圖 ..............................35
圖3-8. 側壁與底部為氮化矽條件，寬度為40 nm的TEM Cross-Section ................................................36
圖3-9. 偶合量子點 .......................................36
圖3-10. 側壁與底部為氮化矽條件的TEM Cross-Section ..37
圖3-11. 側壁為二氧化矽，底部為氮化矽條件的TEM Cross-Section ................................................38
圖3-12. TSUPREM模擬溝渠氧化圖 .....................39
圖3-13. 日本NTT氧化奈米矽線實驗 .....................39
圖3-14. 調變奈米矽線幾何尺寸 .....................40
圖4-1. 結構示意圖 .......................................44
圖4-2. 以金屬當作電極的SET能帶圖，Source電極尚未與ground state達到共振 .......................................44
圖4-3. Source電極與ground state達到共振 ............44
圖4-4. Source電極與多個能階達到共振 .....................45
圖4-5. 以半導體當作電極的SET能帶圖 .....................45
圖4-6. T=300 K之電子電洞能量分佈 .....................46
圖4-7. Source電極無法與任一個能階達到共振 ............46
圖4-8. Source電極與更高的能階達到共振 ............47
圖4-9. RTD電性量測圖VDS-ID ..............................47
圖4-10. 結構plane view示意圖 .....................48
參考文獻 [1] 陳啟東，「單電子電晶體簡介」，物理雙月刊，第二十六卷，第三期，483－490頁，2004年6月。
[2] Y. Takahashi et al., “Silicon single-electron devices and their applications,” inIEEE Int. Symp. ISMVL, p. 411, 2000.
[3] Y. Nakamura, D. L. Klein, and J. S. Tsai, “Al/Al2O3/Al single electron transistors operable up to 30 K utilizing anodization controlled miniaturization enhancement,” Appl. Phys. Lett., Vol. 68, p. 275, 1996.
[4] W. Chen, H. Ahmed and K. Nakazato, “Coulomb blockade at 77 K in nanoscale metallic islands in a lateral nanostructure,” Appl. Phys. Lett., Vol. 66, p. 3383, 1995.
[5] D. L. Klein, P. L. McEuen, J. E. B. Katari, R. Roth, and A. P. Alivisatos,” An approach to electrical studies of single nanocrystals,” Appl. Phys. Lett., Vol. 68, p. 2574, 1996.
[6] Matsumoto, K., “STM/AFM nano-oxidation process to room- temperature- operated single-electron transistor and other devices,” Processdings of the IEEE, Vol. 14, p. 612, 1997.
[7] M. E. Rubin et al., “Imaging and Spectroscopy of Single InAs Self-Assembled Quantum Dots using Ballistic Electron Emission Microscopy,” Phys. Rev. Lett., Vol. 77, p. 5268, 1996.
[8] Yasuo Takahashi, Hideo Namatsu and Kenji Kurihara, “Size Dependence of the characteristics of Si single electron transistors on SIMOX substrates,” Electron Devices IEEE Trans., Vol. 43, p. 1213, 1996.
[9] Masumi Saitoh, Hidehiro Harata, Toshiro Hiramoto, “Room-temperature demonstration of low-voltage and tunable static memory based on negative differential conductance in silicon single-electron transistors,” Appl. Phys. Lett., Vol. 85, p. 6233, 2004.
[10] Sejoon Lee et al., “Extremely high flexibilities of Coulomb blockade and negative differential conductance oscillations in room-temperature-operating silicon single hole transistor,” Appl. Phys. Lett., Vol. 92, p. 073502, 1998.
[11] Effendi Leobandung, Lingjie Guo, Yun Wang, and Stephen Y. Chou, “Single hole quantum dot transistors in silicon,” Appl. Phys. Lett., Vol. 67, p. 2338, 1995
[12] Effendi Leobandung, Lingjie Guo, and Stephen Y. Chou, “Observation of quantum effects and Coulomb blockade in silicon quantum-dot transistors at temperatures over 100 K,” Appl. Phys. Lett., Vol. 67, p. 938, 1995
[13] M. Saitoh, H. Harata and T. Hiramoto, “Room-temperature demonstration of integrated silicon single-electron transistor circuit for current switching and analog pattern matching,” in IEDM Tech Dig., p. 187, 2004.
[14] W. T. Lai and P. W. Li, “Growth kinetics and related physical/electrical properties of Ge quantum dot formed by thermal oxidation of Si1-xGex-on-insulator,” Nanotechnol., Vol. 18, p. 145402, 2007.
[15] P. W. Li, W. M. Liao, David M. T. Kuo, and S. W. Lin, “Fabrication of a germanium quantum-dot single-electron transistor with large Coulomb-blockade oscillations at room temperature,” Appl. Phys. Lett., Vol. 85, p. 1532, 2004.
[16] P. W. Li, David M. T. Kuo, W. M. Liao, and W. T. Lai, “Study of tunneling currents through germanium quantum-dot single-hole and –electron transistors,” Appl. Phys. Lett., Vol. 88, p. 213117, 2006.
[17] Masumi Saitoh and Toshiro Hiramoto, ”Observation of current staircase due to large quantum level spacing in a silicon single-electron transistor with low parasitic series resistance,” J. Appl. Phys., Vol. 91, p. 6725, 2002.
[18] Lei Zhuang, Lingjie Guo, and Stephen Y. Chou, “Silicon single-electron quantum-dot transistor switch operating at room temperature,” Appl. Phys. Lett., Vol. 72, p. 1025, 1998
[19] Masaharu Kobayashi and Toshiro Hiramoto, “Experimental study on quantum confinement effects in silicon nanowire metal-oxide-semiconductor field-effect transistors and single-electron transistors,” J. Appl. Phys, Vol. 103, p. 053709, 2008
[20] 莊達人編著, “VLSI 製造技術”, 第六章.
[21] M. Nagase, A. Fujiwara, K. Yamazaki, Y. Takahashi, K. Murase and K. Kurihara, “Si nanostructures formed by pattern-dependent oxidation,” Microelectronic Engineering, Vol. 41, p. 527, 1998
[22] M. Uematsu , H. Kageshima , K. Shiraishi , M. Nagase,S. Horiguchi a, Y. Takahashi, “Two-dimensional simulation of pattern-dependent oxidation of silicon nanostructures on silicon-on-insulator substrates,” Solid-State Electronics, Vol. 48, p. 1073, 2004
[23] Donald A. Neamen, “Semiconductor Physics & Devices,”
指導教授 李佩雯(Pen-wen Li) 審核日期 2009-1-20 推文 plurk
funp
live
udn
HD
myshare
netvibes
friend
youpush
delicious
baidu
網路書籤 Google bookmarks
del.icio.us
hemidemi
facebook
twitter
google
reddit