參考文獻 |
[1] W.-T. Chen, J.-C. Hsu, H.-W. Lune, and C.-C. Su, “A Spread Spectrum Clock Generator for SATA-II,” in IEEE Int. Symposium on Circuits and Systems Conf. Tech. Papers, 2005, pp. 2643-2646.
[2] H.-R. Lee, O. Kim, G. Ahn, and D. K. Jeong, “A Low Jitter 5000 ppm Spread Spectrum Clock Generator for Multi-channel SATA Transceiver in 0.18um CMOS,” in IEEE Int. Solid-State Circuit Conf. Dig. Tech. Papers, 2005, pp. 160-161.
[3] H.-H. Chang, I.-H. Hua, and S.-I. Liu, “A Spread-Spectrum Clock Generator with Triangular Modulation,” IEEE J. Solid-State Circuits, vol.30, no. 4, pp. 673-676, Apr. 2003.
[4] J. Shin, I. Seo, J.Y. Kim, S.-H. Yang, C. Kim, J. Pak, H. Kim, M. Kwak, and G. Hong, “A Low-Jitter Added SSCG with Seamless Phase Selection and Fast AFC for 3rd Generation Serial-ATA,” in IEEE Custom Integrated Circuits Conf. Tech. Papers, 2006, pp. 409-412.
[5] P.-Y. Wang and S.-P. Chen, “Spread Spectrum Clock Generator,” in IEEE Asian Solid-State Circuits Conf. Tech. Papers, 2007, pp. 304-307.
[6] M. Kokubo, T. Kawamoto, T. Oshima, T. Noto, M. Suzuki, S. Suzuki, T. Hayasaka, T. Takahashi, and J. Kasai, “Spread-Spectrum Clock Generator for Serial ATA Using Fractional PLL Controlled by Δ∑ Modulator with Level Shifter,” in IEEE Int. Solid-State Circuit Conf. Dig. Tech. Papers, 2005, pp. 160-590.
[7] D.-S. Shen and S.-I. Liu, “A Low-Jitter Spread Spectrum Clock Generator Using FDMP,” IEEE Tran. on Circuits And Systems II, vol. 54, no. 11, pp. 979-983, Nov. 2007.
[8] J. Craninckx and M.S.J. Steyaert, “A 1.75-GHz-3-V Dual-Modulus Divide-by-128-129 Pre-scalar in 0.7-um CMOS,” IEEE J. Solid-State Circuits, vol. 31, no. 7 , pp. 890-897, Jul. 1996.
[9] C.-H. Park, O. Kim, and B. Kim, “A 1.8-GHz Self-Calibrated Phase-Locked Loop with Precise I/Q Matching , ” IEEE J. Solid-State Circuits, vol. 36, no. 5, pp. 777-783, May. 2001.
[10] C.-S.Vaucher, I. Ferencic, M. Locher, S. Sedvallson, U. Voegeli, and Z. Wang, ” A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-um CMOS Technology, “ IEEE J. Solid-State Circuits, vol. 35, no. 7 , pp. 1039-1045, May. 2000.
[11] L. W. Couch II, “Digital and Analog Communication Systems,” Macmillan, 1987
[12] K.-B. Hardin, J.-T. Fessler, and D.R. Bush, ”Spread Spectrum Clock Generation for The Reduction of Radiated Emissions,” in IEEE Int. Symposium on Electromagnetic Compatibility Conf. Tech. Papers, 1994, pp. 227 – 231.
[13] L. Xiaomei and S. Mourad, ”Performance of Submicron CMOS Devices and Gates with Substrate Biasing,” in IEEE Int. Symposium on Circuits and Systems Conf. Tech. Papers, 2000, pp. 9 – 12.
[14] S. Narendra, A. Keshavarzi, B.-A. Bloechel, S. Borkar, and V. De, ”Forward Body Bias for Microprocessors in 130-nm,” IEEE J. Solid-State Circuits, vol. 38, no. 5 , pp. 696 - 701, May. 2003.
[15] H.-H. Hsieh and L.-H. Lu, ”A High-Performance CMOS Voltage-Controlled Oscillator for Ultra-Low-Voltage Operations,” IEEE Tran. on Microwave Theory and Techniques, vol. 55, no. 3 , pp. 467 - 473, Mar. 2007.
[16] B. Razavi, ”RF Microelectronics,”1ST Ed., Prentice Hall,1998.
[17] S. Sedra, ”Microelectronic Circuits ,” 5ST Ed., Oxford University Press,2004.
[18] Y.-C. Yang, S.-A. Yu, T. Wang, and S.-S. Lu, ”A Dual-Mode Truly Modular Programmable Fractional Divider Based on a 1/1.5 Divider Cell, ” IEEE Microwave and Wireless Components Letters, vol. 15, no. 11 , pp. 754 - 756, Nov. 2005.
[19] C.-H. Heng and B.-S. Song, ”A 1.8-GHz CMOS Fractional-N Frequency Synthesizer With Randomized Multiphase VCO, ” IEEE J. Solid-State Circuits, vol. 38, no. 6 , pp. 848-854, Jun. 2003.
[20] S.-I. Liu and C.-Y. Yang , “A Phase Locking Loop,” Tsang Hai,2006
[21] Y.-H. Chuang, S.-L. Jang, J.-F. Lee, and S.-H. Lee, “A Low Voltage 900-MHz Voltage Controlled Ring Oscillator With Wide Liming,” in IEEE Asia-Pacific Conf. on Circuits and Systems Tech. Papers, 2004, pp. 301 – 304.
[22] N. Krishnapura and P.-R. Kinget, “A 5.3-GHz Programmable Divider for HiPerLAN in 0.25-um CMOS,” IEEE J. Solid-State Circuits, vol. 35, no. 7 , pp. 1019-1024, Jul. 2000.
[23] X.-P. Yu, M.-A. Do, J.-G. Ma, K.-S. Yeo, R. Wu, and G.-Q. Yan, “ Low Power High-Speed CMOS Dual-Modulus Prescaler Design with Imbalanced Phase-Switching Technique,” IEE Proceedings Circuits Devices and Systems, vol. 152, no. 2 , pp. 127-132, Apr. 2005.
[24] A.-M. Fahim, “A Compact, Low-Power Low- Jitter Digital PLL,” in IEEE European Solid-State Circuits Conf. Tech. Papers, 2003, pp. 101 - 104.
[25] T. Kawamoto and M. Kokubo, “A low-jitter 1.5-GHz and Large-EMI Reduction 10-dBm Spread-Spectrum Clock Generator for Serial-ATA,” in IEEE Asia and South Pacific Design Automation Conf. Tech. Papers, 2009, pp. 696 - 701.
[26] B. Razavi, “Design of Analog CMOS Integrated Circuits,”1ST ED., McGraw-Hill , 2001.
[27] I.-A. Young, J.-K. Greason, J.-E. Smith, and K.-L.Wong, “A PLL Clock Generator with 5 to 110-MHz of Lock Range for Microprocessors,” in IEEE Int. Solid-State Circuit Conf. Dig. Tech. Papers, 1992, pp. 50-51.
[28] R. Mohanavelu and P. Heydari, “A Novel 40-GHz Flip-Flop-Based Frequency Divider in 0.18-um CMOS,” in IEEE European Solid-State Circuits Conf. Tech. Papers, 2005, pp. 185-188.
[29] B. Razavi, “A Study of Injection Locking and Pulling in Oscillators,” IEEE J. Solid-State Circuits, vol. 39, no. 9 , pp. 1415-1424, Jun. 2004.
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