降低鎖相迴路之製程變異敏感度的研究

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姓名

林佩勳(Pei-syun Lin) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

降低鎖相迴路之製程變異敏感度的研究
(On Sensitivity Reduction for Charge-PumpPLLs under Process Variation)

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摘要(中)

隨著製程的演進，積體電路的尺寸已經進入奈米（nanometer）技術的時代。由於製程微縮的影響，製程變異（process variation）與良率損失（yield loss）的議題亦變的不容忽視，尤其是針對較敏感的類比電路。因此積體電路的可行性製造設計（design for manufacturability, DFM）以及以良率為導向（design for yield, DFY）的電路設計概念亦更備受重視。期望在電路設計的階段，就能將電路在實際製造過程中，可能遭受的製程變異現象考慮進來，設計出符合以良率導向為前提的電路設計，不僅能夠免去重新設計電路所需耗費的時程，在經濟效益上也有很大的提升。
本論文是以一個充電幫浦式的鎖相迴路（charge pump phase-locked loop, CPPLL）為研究實例，提出一套可以降低製程變異敏感度的電路調整流程（sensitivity reduction sizing flow），以階層式（hierarchical）的概念，將此調整策略套用在鎖相迴路中對製程變異較為敏感（sensitivity）的類比電路上，針對各電路的幾何參數進行方向性的調整，期望在標稱效能點（nominal performance）近乎維持不變的原則下，達到改善電路對製程敏感度的目的。而反應在鎖相迴路效能層面的良率亦能有不錯的提升。

摘要(英)

Along with the evolution of manufacturing process, the size of integrated circuits has shrunk into the nanometer scale. Process variation and yield loss issues became more and more serious, especially for analog circuits. Therefore, the design-for-manufacturability (DFM) and design-for-yield (DFY) techniques have been widely used to reduce the impacts of those negative effects. If designers can consider the process variation phenomena in early design stages, the design iterations could be shortened significantly to achieve better economical benefit.
In this thesis, we propose a sizing flow for the phase-locked loop circuits with a charge pump to reduce the process sensitivity. Using the hierarchical concept, the geometrical parameters of the sensitivity analog blocks are adjusted for sensitivity reduction with similar nominal performance, the yield of PLL is improved significantly after sensitivity reduction as shown in the experimental results.

關鍵字(中)

★ 鎖相迴路
★ 製程變異敏感度
★ 製程變異

關鍵字(英)

★ sensitivity reduction
★ process variation
★ phase-locked loop
★ process sensitivity

論文目次

第一章序論 ....................................................................................................... 1
1-1 研究動機 ....................................................................................................................... 1
1-2 製程變異敏感度（Process Variation Sensitivity） ..................................................... 2
1-2-1 臨界電壓的變異 ...................................................................................................... 3
1-3 設計中心化 ................................................................................................................... 5
1-4 問題描述 ....................................................................................................................... 6
1-4-1 問題定義 .................................................................................................................. 6
1-4-2 實驗電路 .................................................................................................................. 7
1-4-3 鎖相迴路簡介 .......................................................................................................... 8
1-5 論文組織 ....................................................................................................................... 9
第二章充電幫浦 ............................................................................................... 10
2-1 電路簡介 ..................................................................................................................... 10
2-2 參數定義 ..................................................................................................................... 11
2-3 敏感度分析 ................................................................................................................. 13
v
2-4 電路之幾何參數調整流程（sizing flow） ............................................................... 15
2-4-1尺寸切入調整策略 ................................................................................................. 15
2-4-2偏壓切入調整策略 ................................................................................................. 23
2-5 實驗數據之分析與討論 ............................................................................................. 25
2-5-1 尺寸切入調整策略與偏壓切入調整策略 ............................................................ 25
2-5-2策略重組 ................................................................................................................. 26
2-5-3 加入面積限制 ........................................................................................................ 27
2-6 總結 ............................................................................................................................. 29
第三章壓控振盪器 ........................................................................................... 31
3-1 電路簡介 ..................................................................................................................... 31
3-2 參數定義 ..................................................................................................................... 32
3-3 敏感度分析 ................................................................................................................. 33
3-4 電路之幾何參數調整流程（sizing flow） ............................................................... 35
3-5 實驗數據之分析與討論 ............................................................................................. 38
第四章鎖相迴路之效能評比 ........................................................................... 40
4-1 鎖相迴路效能（Performance） ................................................................................. 40
4-2 鎖相迴路良率（Yield）分析 .................................................................................... 41
第五章結論 ....................................................................................................... 44
參考文獻 ............................................................................................................. 45

參考文獻

[1] C. Guardiani, M. Bertoletti, N. Dragone, M. Malcotti, and P. McNamara, “An Effective DFM Strategy Requires Accurate Process and IP Pre-Characterization,” IEEE Design Automation Conference(DAC), June 2005.
[2] M. Pronath, “Circuit Design for Yield with MunEDA WiCkeD,” MunEDA Technical Forum Taiwan, Apr. 2008.
[3] C. Chiang, J. Lawa, “Design for Manufacturability and Yield for Nano-Scale CMOS,” Springer, 2007.
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[5] D. Kim, C. Cho, J. Kim, J.-O. Plouchart, R. Trzcinski, D. Ahlgren, “CMOS Mixed-Signal Circuit Process Variation Sensitivity Characterization for Yield Improvement,” IEEE Custom Integrated Circuits Conference(CICC), Sept. 2006.
[6] H. Fukutome, Y. Momiyama, T. Kubo, Y. Tagawa, T. Aoyama, and H. Arimoto, “Direct Evaluation of Gate Line Edge Roughness Impact on Extension Profiles in Sub-50-nm n-MOSFETs,” IEEE Transactions on Electron Devices, vol. 53, no. 11, Nov. 2006.
[7] K. Kuhn, C. Kenyon, A. Kornfeld, M. Liu, A. Maheshwari, W.-k. Shih, S. Sivakumar, G. Taylor, P. VanDerVoorn, K. Zawadzki, “Managing Process Variation in Intel’s 45nm CMOS Technology,” Intel Technology Journal, Vol. 12, Issue 2, 2008.
[8] F.-L. Yang, J.-R. Hwang, and Y. Li*, “Electrical Characteristic Fluctuations in Sub-45nm CMOS Devices,” IEEE Custom Integrated Circuits Conference(CICC), Sept. 2006.
[9] M. Meehan, “Understanding and maximising yield through design centering,” IEE Colloquium on Computer Based Tools for Microwave Engineers, Oct. 1991.
[10] 蔡宜青, “以統計分析結果建立鎖相迴路之無邊界式良率優化技術的研究,” 國立中央大學電機工程研究所碩士論文, Jun. 2007.
[11] B. Razavi, “Design of Analog CMOS Integrated Circuits,” McGRAW-HILL International Edition, 2001.
[12] 劉深淵, 楊清淵, “鎖相迴路,” 滄海書局, 2006.
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[13] D. Ghai, S. P. Mohanty, E. Kougianos, “Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) Design,” IEEE International Symposium on Quality Electronic Design (ISQED), 2008.

指導教授

劉建男(Chien-Nan Jimmy Liu)

審核日期

2009-7-16

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