具低相位雜訊之鎖相迴路設計

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：13

、訪客IP：18.191.66.102

姓名

柯幸姍(Hsing-shan Ko) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

具低相位雜訊之鎖相迴路設計
(Design of Low Phase Noise Phase-locked-loop (PLL))

相關論文

★ 一種應用於觸控液晶顯示器的新型嵌入式開關	★ 多重相位之延遲鎖定迴路倍頻器設計與分析
★ 2.5Gbps串列收發器設計	★ 具低抖動與可適應式頻寬之自我偏壓鎖相迴路設計
★ 應用於串列傳輸之2.5GB/s CMOS 超取樣資料回復電路	★ 全數位任意責任週期之同步映射延遲電路
★ 全數位式互補金屬氧化半導自我取樣延遲線電路用於時脈抖動量測	★ 500MHz,30個相位輸出之鎖相迴路應用於三倍超取樣時脈回復系統
★ 設計於90奈米製程輸出頻率為100MHz-1GHz之具可適應性頻寬鎖相迴路	★ 高解析度可變動責任週期之同步複製延遲電路
★ 奈米CMOS晶片內序列傳輸之接收器	★ 奈米CMOS晶片內序列傳輸之送器
★ 基於鎖相迴路之多重相位脈波產生器	★ 低能量時脈儲存元件之分析、設計與量測
★ 具有預先增強器之Gbps串列連結傳送器及全數位超取樣資料回復器	★ 應用於10Gbps晶片系統傳輸鏈之低抖動自我校準鎖相迴路設計

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

近年來晶片皆趨向單晶片系統(System-on-Chip)的方向，在整合系統中各個子電路區塊常出現操作時脈相位不同，而導致輸出資料錯誤，因此需要鎖相迴路(Phase-locked-Loop, PLL)來減少相位偏差，使得整合系統中各個子電路的時脈相位一致，減少輸出誤差。
在時域的應用中，鎖相迴路最常被注意到的性能就是時脈抖動(Jitter)，而在頻域應用中，鎖相迴路最常被注意到的性能就是相位雜訊(Phase Noise)，兩者性能之間可做轉換，在時域上，當時脈抖動愈小時，其頻域上的相位雜訊也會愈好。
在高速的系統中，電路對於雜訊十分敏感，故需有較高的雜訊免疫力才能保證系統的穩定度，有鑑於此，本論文提出具低相位雜訊之鎖相迴路設計，可產生3 GHz的頻率，在論文中將對鎖相迴路系統做詳細的雜訊分析，且解析影響整個系統的雜訊最主要的區塊，並對此區塊再做詳細電路的雜訊分析，藉由上述方式，本論文可提供出一低相位雜訊之鎖相迴路的設計方式。
本晶片以TSMC 0.18 um 1P6M CMOS製程實現，輸出頻率為3 GHz，核心面積為0.034 mm2，所消耗的功率為23.7 mW，迴路鎖定時整體時脈輸出抖動量為3 ps(peak-to-peak)以內，RMS jittetr皆在600 fs以內，鎖定時間為600 ns，其環形電壓控制振盪器(Ring Voltage Control Oscillator, Ring-VCO) 在3GHz情況下的相位雜訊可高達-84.13dBc/Hz。

摘要(英)

The chip changes to integrate SOC. There is often phase error or clock skew which generate asynchronous phenomenon in different sub-circuit blocks. The different phase of operate clock that caused to output data error in integrate system. Hence, it needs Phase-Locked Loop (PLL) for decreasing phase error that make the clock phase is corresponding in order to decrease output data error in sub-circuit of integrate system.
The PLL is application to time domain it’s main performance is jitter. The PLL is application to frequency domain it’s main performance is phase noise. When phase noise is best means jitter is lower.
In high-speed system, the circuit for very sensitive to noise. In this thesis, design of low phase noise is proposed. We analysis PLL noise source and find that main effects noise source block and noise analysis in block circuit.
We use the TSMC 0.18 um 1P6M process with supplying 1.8V voltage in proposed PLL. The reference input frequency is 187.5MHz and the output frequency is 3GHz. The period jitter of output frequency is 3ps (pk-pk) RMS jitter is 600 fs. The power consumption of the proposed PLL is 23.7 mW at 3GHz and the Locking time of the PLL is 600ns. The core area is 0.034mm2.

關鍵字(中)

★ 鎖項迴路
★ 相位雜訊
★ 抖動

關鍵字(英)

★ PLL
★ phase noise
★ jitter

論文目次

摘要........................................................................i
Abstract...............................................................ii
圖目錄................................................................... v
表目錄.................................................................vii
第一章緒論........................................................ 1
1.1 研究動機......................................................................................................................1
1.2 論文架構......................................................................................................................2
第二章鎖相迴路基本觀念................................ 3
2.1 鎖相迴路架構及操作原理..........................................................................................3
2.1.1 相位頻率偵測器(Phase Frequency Detector, PFD) .................................4
2.1.2 充電泵(Charge Pump, CP) ..........................................................................5
2.1.3 迴路濾波器(Loop Filter)................................................................................8
2.1.4 電壓控制振盪器(Voltage Control Oscillator)..............................................8
2.2 鎖相迴路的轉移函數分析........................................................................................ 11
第三章鎖相迴路的雜訊分析.......................... 18
3.1 鎖相迴路雜訊的基本分析[10] ................................................................................18
3.1.1 電壓控制振盪器的雜訊................................................................................19
3.1.2 輸入的雜訊....................................................................................................20
3.2 迴路中各組件之雜訊分析[11]-[12] ........................................................................20
3.3 電壓控制振盪器相位雜訊分析................................................................................22
3.3.1 電壓控制振盪器之相位雜訊.......................................................................23
3.3.2 單端環型電壓控制振盪器之相位雜訊[15].................................................24
第四章鎖相迴路設計流程.............................. 32
4.1 鎖相迴路設計流程...................................................................................................32
4.2 論文採用電壓控制振盪器之架構分析與設計.......................................................33
4.2.1 論文採用電壓控制振盪器之架構分析.......................................................33
4.2.2 電路設計與其模擬結果...............................................................................34
4.3 改善架構討論與其模擬結果...................................................................................38
4.3 鎖相迴路設計考量...................................................................................................44
第五章晶片實現與模擬結果.......................... 46
5.1 鎖相迴路各組件模擬結果.......................................................................................46
5.1.1 相位頻率偵測器(PFD).................................................................................46
5.1.2 充電泵(CP)與迴路濾波器(LF)....................................................................48
5.1.3 頻率除頻器(FD) ...........................................................................................49
5.2 鎖相迴路模擬結果...................................................................................................51
5.3 晶片佈局及電路規格比較與討論...........................................................................53
第六章結論....................................................... 58
6.1 結論...........................................................................................................................58
6.2 未來改進方向...........................................................................................................58
參考文獻............................................................. 59

參考文獻

[1] A. Demir, “Phase noise and timing Jitter in oscillators with colored-noise sources”,
IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 49, no. 12,pp. 1782-1791,
Dec. 2002.
[2] R. Poore. (2001, May.). Agilent EEs of EDA. “Phase noise and jitter”. Agilent
Technologies.
[3] J.G.. Maneatis, “Low-jitter process-pndependent DLL and PLL based on
self-biased techniques,” IEEE J. Solid-State Circuits, vol. 31, pp. 1723-1732, Nov.
1996.
[4] W. Rhee, “Design of high-performance CMOS charge pumps in phase-locked
loops”, IEEE International Symposium on Circuits and Systems, vol. 2, pp. 545-548,
Jun. 1999.
[5] B. Razavi, “Design of analog CMOS integrated circuits”, New York：McGraw-Hill,
2001.
[6] T.C. Lee and B. Razavi, "A stabilization technique for phase-pocked frequency
synthesizers", IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 888-894 , Jun. 2003.
[7] 劉深淵, 楊清淵, 鎖相迴路, 滄海書局, 2006
[8] J. Rogers, C. Plett, F. Dai , "Integrated circuit design for high-speed frequency
synthesis", 2006.
[9] W. O. Keese, "An analysis and performance evaluation of a passive filter design
techniques for charge pumps PLL’s", National Semiconductor application note, July
2001.
[10] B. Razavi, “A Study of Phase Noise in CMOS Oscillators", IEEE J. Solid-State
Circuits, vol. 31, no. 3, pp. 331-343, Mar. 1996.
[11] C.H. Lee, K. McClellan, and J. Choma, “A supply noise insensitive PLL design
through PWL behavioral modeling and simulation", IEEE Trans. Circuits Syst. II,
Analog Digit. Signal Process", vol. 48, no. 12, pp. 1137-1144, Dec. 2001
[12] X. Gao, , E. M. Klumperink ,P. F. J. Geraedts, and B. Nauta, “Jitter analysis and a
benchmarking figure-of-merit for phase-pocked loops", IEEE Trans. Circuits Syst. II,
Exp. Briefs, vol. 56, no. 2, pp. 117-121, Feb. 2009
[13] W. B. Wilson, U.K. Moon, K. R. Lakshmikumar, and L. Dai, " A CMOS
self-calibrating frequency synthesizer ", IEEE J. Solid-State Circuits, vol. 35, no.
10,pp.1437-1444, Oct. 2000
[14] 許敦智. “0.18um 互補式金氧半導體高頻壓控振盪器與鎖相迴路設計",國立交通大
學電信工程學系碩士論文, 2006
[15] A. Hajimiri, S. Limotyrakis, and T. H. Lee, “Jitter and phasepoise in ring
oscillators" IEEE J. Solid-State Circuits, vol. 34, pp. 790-804, no. 6, Jun.1999
[16] J. Maneatis, “Low-jitter process-independent DLL and PLL based on
self-biased technique", IEEE J. Solid-State Circuits , vol.31, no.11,pp.1723-1732,
Nov.1996.
[17] W. S. T. Yan and H. C. Luong, “A 900-MHz CMOS Low-Phase-Noise
Voltage-Controlled Ring Oscillator", IEEE Trans. Circuits Syst. II, Analog Digit. Signal
Process., vol. 48, no. 2, pp.216-221, Feb. 2001
[18] J. D. Tang, ,D. Kasperkovitz, and A. Roermund, “A 9.8–11.5 GHz quadrature ring
oscillator for optical receivers ", IEEE J. Solid-State Circuits , vol.37,no.3, pp.438-442,
Mar.2002.
[19] S. Kim, K. Lee, Yong. Moon, D-K Jeong, Y.C., and H.K. Lim, “A 960-Mb/s/pin
interface for skew-tolerant bus using low kitter PLL", IEEE J. Solid-State Circuits, vol.
32, no.5, pp. 691-700, May, 1997.
[20] C.H. Park, O. Kim, and B. Kim, “A 1.8 GHz self-calibrated phase-locked loop with
precise I/Q matching", IEEE J. Solid-State Circuits, vol. 36, no. 5, pp.777-783, May
2001.
[21] Z. Shu, K.L. Lee, and B. H. Leung, “A 2.4 GHz ring-oscillator-based CMOS
frequency synthesizer with a fractional divider dual-PLL architecture", IEEE J.
Solid-State Circuits, vol. 39, no. 3, pp.452-462, Mar.2004.
[22] T. Wu, K. Mayaram, and Un-Ku Moon, “An on-chip calibration technique for
reducing supply voltage sensitivity in ring oscillators", IEEE J. Solid-State Circuits, vol.
42, no. 4, pp.775-783, Apr. 2007

指導教授

鄭國興

審核日期

2009-7-31

推文